GatesAir Inc. CZF 사용자 설명서
APEX
™
Exciter Incorporating FLO
™
Technology
Navigating the LCD Display Screens
Details of the System Setup Screens
Page: 3-50
888-2604-001
03/08/07
WARNING: Disconnect primary power prior to servicing.
3.6.7.3
FPGA Configure 3/5
FPGASetup3.bmp
Figure 3-42 FPGA Configure 3/5
FPGA Configure 3/5 consists of registers whose values are written immediately to the
FPGA when changed through the GUI.
FPGA when changed through the GUI.
FPGA re-initialization shall occur automatically after any of these registers are changed.
The parameters of the FPGA Configure 3/5 screen are as follows.
• Transmitter Delay: (Time in microseconds – see below for calculations)
• NTWK Geog Delay: (Time in microseconds – see below for calculations)
The value for Transmitter Delay shall be displayed in integer microseconds with a valid
range and the value for the FPGA register value calculated (rounded up to the next integer
value) as shown in the following table:
range and the value for the FPGA register value calculated (rounded up to the next integer
value) as shown in the following table:
The value for Network Geographic Delay shall be displayed in integer microseconds with
a valid range and the value for the FPGA register value calculated (rounded up or down to
the next integer value) as shown in the following table:
a valid range and the value for the FPGA register value calculated (rounded up or down to
the next integer value) as shown in the following table:
Bandwidth
Value Range
(in u seconds)
FPGA Register
5 MHz
0 - 221
Value * 37.0
6 MHz
0 - 184
Value * 44.4
7 MHz
0 - 158
Value * 51.8
8 MHz
0 - 137
Value * 59.2
Bandwidth
Value Range
(in u seconds)
FPGA Register
5 MHz
-220 - +221
Value * 37.0
6 MHz
-183 - +184
Value * 44.4
7 MHz
-157 - +158
Value * 51.8
8 MHz
-136 - +137
Value * 59.2