Xi'an NovaStar Tech Co. Ltd T3 사용자 설명서
RTL8188EUS
Datasheet
7. Interface Timing Specification
7.1.
USB Bus during Power On Sequence
3.3V
T
on
T
P OR
T
attach
T
k-state
Card Detection
D+
D-
SE0 Reset
POR
Figure 5. RTL8188EUS USB Bus Power On Sequence
T
on
: The main power ramp up duration
T
por
: The power on reset releases and power management unit executes power on tasks
T
attach
: USB attach state
T
k-state
: the duration from resister attached to USB host starting card detection procedure
The power on flow description:
After main 3.3V ramp up, the internal power on reset is released by power ready detection circuit and the power management
unit will be enabled. The power management unit enables the internal regulator and clock circuits.
The power management unit also enables the USB circuits.
USB analog circuits attach resisters to indicate the insertion of the USB device
Table 11. The typical timing range
Unit
Min
Typical
Max
T
on
ms -- 1.5 5
T
por
ms -- 2 10
T
attach
ms 2 7 15
T
k-state
ms 50 250 --
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
13
Track ID: JATR-2265-11 Rev. 0.1
with USB Interface
Realtek confidential files
The document authorized to
G.M.I
2012-05-21 17:34:48