Intel III Xeon 500 MHz 80525KX5001M 사용자 설명서
제품 코드
80525KX5001M
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
11
•
Pentium
®
II Xeon™ Processor Support Component Vendor List (http://developer.intel.com/
design/pentiumii/xeon/components/)
•
Intel Architecture Software Developer's Manual (Order Number 243193)
— Volume I: Basic Architecture (Order Number 243190)
— Volume II: Instruction Set Reference (Order Number 243191)
— Volume III: System Programming Guide (Order Number 243192)
•
330-Contact Slot Connector (SC330) Design Guidelines (Order Number 244428)
•
VRM 8.2 DC–DC Converter Design Guidelines (www.developer.intel.com)
•
VRM 8.3 DC–DC Converter Design Guidelines, rev 1.0 (Order Number 243870)
•
Intel
®
Pentium
®
III
Processor Bus Terminator Design Guidelines (Order Number 245099)
•
Pentium
®
III
Xeon™ Processor/Intel
®
450NX PCIset AGTL+ Layout Guidelines (Order
Number 245097)
•
100 MHz 2-Way SMP Pentium
®
III
Xeon™ Processor/Intel
®
440GX AGPset AGTL+ Layout
Guidelines (Order Number 245096)
•
P6 Family of Processors Hardware Developer's Manual (Order Number 244001)
•
Pentium
®
II Processor Developer’s Manual (Order Number 243502)
•
Pentium
®
III
Xeon™ Processor SMBus Thermal Reference Guidelines (Order Number
245098)
•
Intel
®
Processor Serial Number (Order Number 245119)
Most or all of this documentation can be found on Intel’s developer’s world wide web site:
www.developer.intel.com.
www.developer.intel.com.
2.0
Electrical Specifications
2.1
The Pentium
®
III Xeon™ Processor System Bus and V
REF
Most Pentium
III
Xeon processor signals use a variation of the Pentium Pro processor GTL+
signaling technology. The Pentium
III
Xeon processor differs from the Pentium Pro processor in its
output buffer implementation. The buffers that drive most of the system bus signals on the Pentium
III
Xeon processor are actively driven to
CCCORE
for one clock cycle after the low to high
transition to improve rise-times and reduce noise. These signals should still be considered open-
drain and require termination to a supply that provides the high signal level. Because this
specification is different from the GTL+ specification, it is referred to as Assisted Gunning
Transistor Logic (AGTL+) in this document. AGTL+ logic and GTL+ logic are compatible with
each other and may both be used on the same system bus. Also refer to the Pentium
drain and require termination to a supply that provides the high signal level. Because this
specification is different from the GTL+ specification, it is referred to as Assisted Gunning
Transistor Logic (AGTL+) in this document. AGTL+ logic and GTL+ logic are compatible with
each other and may both be used on the same system bus. Also refer to the Pentium
®
II Processor
Developer’s Manual for the GTL+ buffer specification.
AGTL+ inputs use differential receivers which require a reference signal (V
REF
). V
REF
is used by
the receivers to determine if a signal is a logical 0 or a logical 1. The Pentium
III
Xeon processor
generates its own version of V
REF
. V
REF
must be generated on the baseboard for other devices on
the AGTL+ system bus. Termination is used to pull the bus up to the high voltage level and to
control signal integrity on the transmission line. The processor contains termination resistors that
control signal integrity on the transmission line. The processor contains termination resistors that