Intel i7-3920XM Extreme AW8063801009607 사용자 설명서
제품 코드
AW8063801009607
Datasheet, Volume 2
175
Processor Configuration Registers
2.10.18 PMLIMIT—Prefetchable Memory Limit Address Register
This register in conjunction with the corresponding Upper Limit Address register
controls the processor to PCI Express-G prefetchable memory access routing based on
the following formula:
controls the processor to PCI Express-G prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1 MB aligned memory block.
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1 MB aligned memory block.
Note:
Prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (that is, prefetchable) from the processor perspective.
B/D/F/Type:
0/6/0/PCI
Address Offset:
26–27h
Reset Value:
0001h
Access:
RW, RO
Size:
16 bits
Bit
Access
Reset
Value
RST/
PWR
Description
15:4
RW
000h
Uncore
Prefetchable Memory Address Limit (PMLIMIT)
This field corresponds to A[31:20] of the upper limit of the
This field corresponds to A[31:20] of the upper limit of the
address range passed to PCI Express-G.
3:0
RO
1h
Uncore
64-bit Address Support (AS64B)
This field indicates that the upper 32 bits of the prefetchable
This field indicates that the upper 32 bits of the prefetchable
memory region limit address are contained in the Prefetchable
Memory Base Limit Address register at 2Ch