Intel SC5299UP SC5299UPNA 사용자 설명서

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Power Sub-system 
Intel
®
 Entry Server Chassis SC5299-E TPS 
  
Revision 
3.1 
Intel order number D37594-005 
18 
 
2.1.5.5 
Voltage Regulation 
The power supply output voltages are within the following voltage limits when operating at 
steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise. 
All outputs are measured with reference to the return remote sense signal (ReturnS). The 5V, 
12V1, 12V2, –12V and 5VSB outputs are measured at the power supply connectors referenced 
to ReturnS. The +3.3V is measured at the remote sense signal (3.3VS) located at the signal 
connector. 
Table 12. Voltage Regulation Limits 
Parameter 
Tolerance 
MIN 
NOM 
MAX 
Units 
+ 3.3V 
- 5%/+5% 
+3.135 
+3.30 
+3.47 
V
rms
 
+ 5V 
- 4%/+5% 
+4.80 
+5.00 
+5.25 
V
rms
 
+ 12V1 
- 5%/+5% 
+11.40 
+12.00 
+12.60 
V
rms
 
+ 12V2 
- 5%/+5% 
+11.40 
+12.00 
+12.60 
V
rms
 
- 12V 
- 5%/+4% 
-11.52 
-12.00 
-12.60 
V
rms
 
+ 5VSB 
- 4%/+5% 
+4.80 
+5.00 
+5.25 
V
rms
 
 
2.1.5.6 
Dynamic Loading 
The output voltages are within limits specified for the step loading and capacitive loading 
specified in the following table. The 
   step load may occur anywhere within the MIN load to the 
MAX load conditions. 
Table 13. Transient Load Requirements 
Parameter 
Output Range 
MAX Step 
Voltage Overshoot/Undershoot  
+12V1DC 
0.5A TO 18A 
6A 
  350mV (700mVpk-pk) 
+12V2DC 
0.5A TO 15A 
6A 
  350mV (700mVpk-pk) 
+5VDC 
2A TO 20A 
5A 
  200mV(400mVpk-pk) 
+3.3VDC 
0.5A TO 17A 
6A 
  200mV (400mVpk-pk) 
+5VSB 
0.1A TO 2.0A 
0.7A 
  250mV(500mVpk-pk)