Intel SC5299UP SC5299UPNA 사용자 설명서
제품 코드
SC5299UPNA
Power Sub-system
Intel
®
Entry Server Chassis SC5299-E TPS
Revision
3.1
Intel order number D37594-005
72
2.4.3.4
DC/DC Converters Ripple/Noise
The maximum allowed ripple/noise output of each DC/DC Converter is defined in the following
table. This is measured over a bandwidth of 0Hz to 20MHz at the PDB output connectors. A
10
table. This is measured over a bandwidth of 0Hz to 20MHz at the PDB output connectors. A
10
F tantalum capacitor in parallel with a 0.1 F ceramic capacitor is placed at the point of
measurement.
Table 88. Ripple and Noise
+3.3V Output
+5V Output
-12V Output
50mVp-p 50mVp-p 120mVp-p
Note: Refer to the Power Supply specification for the equivalent data on +12V and +5VSB output.
2.4.3.5
Fan Operation in Standby Mode
The fans on the power distribution board continue to operate at their lowest speed (5V) when in
standby mode.
standby mode.
2.4.3.6
Timing Requirements
The timing requirements for the power supply/PDB combination are as follows. The output
voltages must rise from 10% to within regulation limits (T
voltages must rise from 10% to within regulation limits (T
vout_rise
) within 5 to 70 ms, except for
5VSB, which is allowed to rise from 1.0 to 25 ms. The +3.3V, +5V, and +12V output voltages
start to rise at approximately the same time. All outputs rise monotonically. The +5V output is
greater than the +3.3V output during any point of the voltage rise. The +5V output is never
greater than the +3.3V output by more than 2.25V. Each output voltage reaches regulation
within 50ms (T
start to rise at approximately the same time. All outputs rise monotonically. The +5V output is
greater than the +3.3V output during any point of the voltage rise. The +5V output is never
greater than the +3.3V output by more than 2.25V. Each output voltage reaches regulation
within 50ms (T
vout_on
) of each other during turn on of the power supply. Each output voltage falls
out of regulation within 400 msec (T
vout_off
) of each other during turn off. The following figure
shows the timing requirements for the power supply being turned on and off via the AC input,
with PSON held low and the PSON signal, with the AC input applied.
with PSON held low and the PSON signal, with the AC input applied.
Table 89. Output Voltage Timing
Item
Description
Minimum
Maximum
Units
T
vout_rise
Output voltage rise time from each main output.
5.0*
70*
msec
T
vout_on
All main outputs must be within regulation of each
other within this time.
other within this time.
50
msec
T
vout_off
All main outputs must leave regulation within this
time.
time.
400
msec
* The 5VSB output voltage rise time shall be from 1.0 ms to 25.0 ms.