Intel SC5299UP SC5299UPNA 사용자 설명서
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SC5299UPNA
Intel
®
Entry Server Chassis SC5299-E TPS
Power Sub-system
Revision 3.1
Intel order number D37594-005
79
2.4.6
PSMI (Power Supply Monitoring Interface)
The power supply and cage combination provide a monitoring interface to the system over a
server management bus to the system. The device is compatible with both SMBus 2.0 ‘high
power’ and I
server management bus to the system. The device is compatible with both SMBus 2.0 ‘high
power’ and I
2
C V
dd
based power and drive. This bus operates at 3.3V. The SMBus pull-ups are
located on the server board.
The SMBUS provides power monitoring, failure conditions, warning conditions, and FRU data.
Two pins have been reserved on the connector to provide this information. One pin is the Serial
Clock (PSM Clock). The second pin is used for Serial Data (PSM Data). Both pins are bi-
directional and are used to form a serial bus. The circuits inside the power supply are powered
from the 5VSB bus and grounded to ReturnS (remote sense return). No pull-up resistors are on
SCL or SDA inside the power supply. These pull-up resistors are located external to the power
supply. The EEPROM for FRU data in the power supply is hard wired to allow writing data to the
device.
Two pins have been reserved on the connector to provide this information. One pin is the Serial
Clock (PSM Clock). The second pin is used for Serial Data (PSM Data). Both pins are bi-
directional and are used to form a serial bus. The circuits inside the power supply are powered
from the 5VSB bus and grounded to ReturnS (remote sense return). No pull-up resistors are on
SCL or SDA inside the power supply. These pull-up resistors are located external to the power
supply. The EEPROM for FRU data in the power supply is hard wired to allow writing data to the
device.
Default Mode Operation: The LEDs and registers automatically clear when a warning event has
occurred. Critical events will cause the power supply to shut down and latch the LED and
SMBAlert signal. A warning event will allow the LED and SMBAlert signal to de-assert as soon
as the condition driving the event clears.
occurred. Critical events will cause the power supply to shut down and latch the LED and
SMBAlert signal. A warning event will allow the LED and SMBAlert signal to de-assert as soon
as the condition driving the event clears.
The LED, SMBAlert signal, and critical event registers will still operate correctly if the power
supply fails due to over-temperature shut down, over-current shutdown, over-power shutdown,
or fan failure. If the power supply fails due to loss of AC or open fuse then the LED and signals
will not operate because of loss of power.
supply fails due to over-temperature shut down, over-current shutdown, over-power shutdown,
or fan failure. If the power supply fails due to loss of AC or open fuse then the LED and signals
will not operate because of loss of power.
2.4.6.1
Device Address Locations
The PS+PDB device address locations are shown in the following table.
Table 96. Device Address Locations
Power Supply FRU Device
A0h/A2h
PDB FRU Data
Ach
PBD Monitoring
4Ah
2.4.6.2
Summary of PSMI features for PDB
Item
Description
Scaling
Accuracy
Associated Registers
Fan
monitoring
monitoring
A slow fan indication shall be provided
before the power supply shuts down
due to slowing fan failure. Hysteresis
on the fan monitoring shall be
provided to prevent oscillation of the
warning indicator.
before the power supply shuts down
due to slowing fan failure. Hysteresis
on the fan monitoring shall be
provided to prevent oscillation of the
warning indicator.
TBD
NA
Event register bit
Mask register bit