Intel G550T CM8062301002309 사용자 설명서
제품 코드
CM8062301002309
Datasheet, Volume 2
247
Processor Configuration Registers
2.18.24 IEDATA_REG—Invalidation Event Data Register
This register specifies the Invalidation Event interrupt message data. This register is
treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
2.18.25 IEUADDR_REG—Invalidation Event Upper Address
Register
This register specifies the Invalidation Event interrupt message upper address.
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
A40000_0–A7h
Reset Value:
0000_0000h
Access:
RW-L
Size:
32 bits
Bit
Attr
Reset
Value
RST/
PWR
Description
31:16
RW-L
0000h
Uncore
Extended Interrupt Message Data (EIMD)
This field is valid only for implementations supporting 32-bit
This field is valid only for implementations supporting 32-bit
interrupt data fields.
Hardware implementations supporting only 16-bit interrupt data
Hardware implementations supporting only 16-bit interrupt data
treat this field as RsvdZ.
15:0
RW-L
0000h
Uncore
Interrupt Message data (IMD)
Data value in the interrupt request.
Data value in the interrupt request.
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
AC–AFh
Reset Value:
0000_0000h
Access:
RW-L
Size:
32 bits
Bit
Attr
Reset
Value
RST/
PWR
Description
31:0
RW-L
00000000h
Uncore
Message Upper Address (MUA)
Hardware implementations supporting Queued Invalidations and
Hardware implementations supporting Queued Invalidations and
Extended Interrupt Mode are required to implement this register.
Hardware implementations not supporting Queued Invalidations or
Hardware implementations not supporting Queued Invalidations or
Extended Interrupt Mode may treat this field as reserved.