Hynix 4GB DDR3 PC3-12800 HMT351R7CFR4C-PB 사용자 설명서
제품 코드
HMT351R7CFR4C-PB
Rev. 1.0 / Jul. 2012
63
Table 9 - IDD5B Measurement-Loop Pattern
a)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
CK, CK
CKE
Sub
-Loop
Cy
cle
Number
Command
CS
RAS
CAS
WE
OD
T
BA[
2
:0]
A[1
5
:1
1]
A[1
0
]
A
[9:7]
A
[6:3]
A[2
:0]
Data
b)
toggling
Static High
0
0
REF
0
0
0
1
0
0
0
0
0
0
0
-
1
1.2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
3,4
D, D
1
1
1
1
0
0
00
0
0
F
0
-
5...8
repeat cycles 1...4, but BA[2:0] = 1
9...12
repeat cycles 1...4, but BA[2:0] = 2
13...16
repeat cycles 1...4, but BA[2:0] = 3
17...20
repeat cycles 1...4, but BA[2:0] = 4
21...24
repeat cycles 1...4, but BA[2:0] = 5
25...28
repeat cycles 1...4, but BA[2:0] = 6
29...32
repeat cycles 1...4, but BA[2:0] = 7
2
33...nRFC-1
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.