Intel E7-8891 v2 CM8063601377422 사용자 설명서
제품 코드
CM8063601377422
Processor Uncore Configuration Registers
102
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
30:28
RW
0x0
MH1_DIMM_CID (mh1_dimm_cid):
Hottest DIMM Channel ID for MEM_HOT[1]#. PCU microcode search the
hottest DIMM temperature and write the hottest temperature and the
corresponding Hottest DIMM CID/ID.
000 - Channel0
001 - Channel1
010 - Channel2
011 - Channel3
100- 111 Reserved.
000 - Channel0
001 - Channel1
010 - Channel2
011 - Channel3
100- 111 Reserved.
27:24
RW
0x0
MH1_DIMM_ID (mh1_dimm_id):
Hottest DIMM ID for MEM_HOT[1]#. PCU microcode search the hottest
DIMM temperature and write the hottest temperature and the
corresponding Hottest DIMM CID/ID.
000 - DIMM0
001 - DIMM1
010 - DIMM2
011- 111 Reserved.
000 - DIMM0
001 - DIMM1
010 - DIMM2
011- 111 Reserved.
23:16
RW
0x0
MH1_TEMP (mh1_temp):
Hottest DIMM Sensor Reading for MEM_HOT[1]# - This reading represents
the temperature of the hottest DIMM. PCU microcode search the hottest
DIMM temperature and write the hottest temperature and the
corresponding Hottest DIMM CID/ID. Note: iMC hardware load this value
into the MEMHOT duty cycle generator counter since PCU microcode may
update this field at different rate/time. This field is ranged from 0 to 127,
i.e. the most significant bit is always zero.
15:15
RW_V
0x0
MH0_DIMM_VAL (mh0_dimm_val):
Valid if set. PCU microcode search the hottest DIMM temperature and write
the hottest temperature and the corresponding Hottest DIMM CID/ID and
set the valid bit. MEMHOT hardware logic process the corresponding
MEMHOT data when there is a MEMHOT event. Upon processing, the valid
bit is reset. PCU microcode can write over existing valid temperature since a
valid temperature may not occur during a MEMHOT event. If PCU microcode
set the valid bit occur at the same cycle that the MEMHOT logic processing
and try to clear, the PCU microcode set will dominate since it is a new
temperature is updated while processing logic tries to clear an existing
temperature.
14:12
RW
0x0
MH0_DIMM_CID (mh0_dimm_cid):
Hottest DIMM Channel ID for MEM_HOT[0]#. PCU microcode search the
hottest DIMM temperature and write the hottest temperature and the
corresponding Hottest DIMM CID/ID.
000 - Channel0
001 - Channel1
010 - Channel2
011 - Channel3
100- 111 Reserved.
000 - Channel0
001 - Channel1
010 - Channel2
011 - Channel3
100- 111 Reserved.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x120
Bit
Attr
Default
Description