Intel E7-8891 v2 CM8063601377422 사용자 설명서
제품 코드
CM8063601377422
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
129
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.4.6
PMONUNITSTATUS
This field shows which registers have overflowed in the unit.
Whenever a register overflows, it should set the relevant bit to 1. An overflow should
not effect the other status bits. This status should only be cleared by software.
not effect the other status bits. This status should only be cleared by software.
We have defined 7 bits for this status. This is overkill for many units. See below for the
bits that are used in the different units.
bits that are used in the different units.
In general, if the unit has a fixed counter, it will use bit 0. Counter 0 would use the next
LSB, and the largest counter would use the MSB.
LSB, and the largest counter would use the MSB.
HA: [4:0] w/ [4] = Counter4 and [0] = Counter 0
iMC: [5:0] w/ [0] = Fixed; 1 = Counter0 and 5 = Counter4
Intel
®
QPI: [4:0] (same as HA)
PCU: [3:0]: [0] = Counter0 and [3] = Counter 3
IO IRP0: [0] = Counter0; [1] = Counter1
IO IRP1: [2] = Counter0; [3] = Counter1
13.2.4.7
PXPENHCAP
This field points to the next Capability in extended configuration space.
0:0
WO
0x0
Reset Counter Configs (resetcounterconfigs):
When this bit is written to, the counter configuration registers will be reset. This
does not effect the values in the counters.
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device: 30
Function:
0,1,4,5
Offset:
0xf4
Bit
Attr
Default
Description
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Offset:
0xf8
Bit
Attr
Default
Description
31:7
RV
-
Reserved.
6:0
RW1C
0x0
Counter Overflow Bitmask (counteroverflowbitmask):
This is a bitmask that specifies which counter (or counters) have overflowed.
If the unit has a fixed counter, its corresponding bitmask will be stored at
position 0.