Intel E7-8891 v2 CM8063601377422 사용자 설명서

138

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

26:24

RW

0x2

T_RWSR (t_rwsr):

This field is used as read ODT delay bits 2:0 in Intel® Xeon® Processor E7-

2800/4800/8800 v2 Product Family. Refer to TCOTHP2 for the new register 

field location for T_RWSR.

23:21

RW

0x2

T_WRDD (t_wrdd):

Back to back WRITE to READ from different DIMM separation parameter.The 

actual WRITE to READ command separation is

TCDBP.T_CWL - TCDBP.TCL + T_WRDD + 6 DCLKs measured between the 

clock assertion edges of the two corresponding asserted command CS#.

20:18

RW

0x2

T_WRDR (t_wrdr):

Back to back WRITE to READ from different RANK separation parameter.The 

actual WRITE to READ command separation is

TCDBP.T_CWL - TCDBP.TCL + T_WRDR + 6 DCLKs measured between the 

clock assertion edges of the two corresponding asserted command CS#.

17:15

RW

0x2

T_RWDD (t_rwdd):

This field is not used starting in Intel® Xeon® Processor E7-

2800/4800/8800 v2 Product Family. Refer to TCOTHP2 for the new register 

field location.

14:12

RW

0x2

T_RWDR (t_rwdr):

Bits 2:1 of this field is not used starting in Intel® Xeon® Processor E7-

2800/4800/8800 v2 Product Family. Refer to TCOTHP2 for the new register 

field location of T_RWDR.
Bit 0 of this field is used as bit 3 of read ODT delay. Find bits 2:0 of read 

ODT delay in T_RWSR field of this register.

11:9

RW

0x2

T_WWDD (t_wwdd):

Back to back WRITE to WRITE from different DIMM separation parameter. 

The actual WRITE to WRITE command separation is

T_WWDD + 5 DCLKs measured between the clock assertion edges of the 

two corresponding asserted command CS#. Note that the minimum setting 

of the field must meet the DDRIO requirement for WRITE to WRITE 

turnaround time to be at least 6 DClk at the DDRIO pin.

The maximum design range from the above calculation is 15.

8:6

RW

0x2

T_WWDR (t_wwdr):

Back to back WRITE to WRITE from different RANK separation parameter. 

The actual WRITE to WRITE command separation is

T_WWDR + 5 DCLKs measured between the clock assertion edges of the 

two corresponding asserted command CS#. Note that the minimum setting 

of the field must meet the DDRIO requirement for WRITE to WRITE 

turnaround time to be at least 6 DClk at the DDRIO pin.

The maximum design range from the above calculation is 15.