Intel E7-8891 v2 CM8063601377422 사용자 설명서

140

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

Timing Constraints DDR3 Refresh Parameter. 

Timing Constraints Refresh Timing Parameter. 

10:8

RW

0x0

T_CWL_ADJ (t_cwl_adj):

This register defines additional WR data delay per channel in order to overcome 

the WR-flyby issue.
The total CAS write latency that the DDR sees is the sum of T_CWL and the 

T_CWL_ADJ.
000 - no added latency  (default)
001 - 1 Dclk of added latency
010 - 2 Dclk of added latency
011 - 3 Dclk of added latency
1xx - Reduced latency by 1 Dclk. Not supported at tCWL = 5

7:5

RW

0x3

T_XP (t_xp):

Exit Power Down with DLL on to any valid command; Exit Precharge Power 

Down with DLL frozen to commands not requiring a locked DLL.

4:0

RW

0xa

T_XPDLL (t_xpdll):

Exit Precharge Power Down with DLL frozen to commands requiring a locked 

DLL.

31:16

RV

-

Reserved.

15:12

RW

0x9

REF_PANIC_WM (ref_panic_wm):

tREFI count level in which the refresh priority is panic (default is 9)
It is recommended to set the panic WM at least to 9, in order to utilize the 

maximum no-refresh period possible

11:8

RW

0x8

REF_HI_WM (ref_hi_wm):

tREFI count level that turns the refresh priority to high (default is 8)

7:0

RW

0x3f

OREFNI (orefni):

Rank idle period that defines an opportunity for refresh, in DCLK cycles