Intel E7-8891 v2 CM8063601377422 사용자 설명서

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

209

Datasheet Volume Two: Functional Description, February 2014

Interrupt Line Register.

Interrupt Pin Register.

Bridge Control Register.

7:0

RW

RO (Device 0 

Function 0)

0x0

interrupt_line:

N/A for these devices

7:0

RW_O

0x1

intp:

N/A since these devices do not generate any interrupt on their own

15:7

RV

-

Reserved. 

6:6

RW

0x0

sbr:

1: Setting this bit triggers a hot reset on the link for the corresponding PCI 

Express port and the PCI Express hierarchy domain subordinate to the port. 

This sends the LTSSM into the Training (or Link) Control Reset state, which 

necessarily implies a reset to the downstream device and all subordinate 

devices. The transaction layer corresponding to port will be emptied by virtue 

of the link going down when this bit is set. This means that in the outbound 

direction, all posted transactions are dropped and nonposted transactions are 

sent a UR response. In the inbound direction, completions for inbound NP 

requests are dropped when they arrive. Inbound posted writes are retired 

normally.Note also that a secondary bus reset will not reset the virtual PCI-

to-PCI bridge configuration registers of the targeted PCI Express port.
0: No reset happens on the PCI Express port.

5:5

RV

-

Reserved.