Intel E7-8891 v2 CM8063601377422 사용자 설명서

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

325

Datasheet Volume Two: Functional Description, February 2014

Power Management Capability.

The PM Capabilities Register defines the capability ID, next pointer and other power 
management related support. The following PM registers /capabilities are added for 
software compliance.

Power Management Control and Status.

This register provides status and control information for PM events in the PCI Express 
port of the IIO.

31:27

RO

0x0

pme_support:

Bits 31, 30 and 27 must be ‘0’. PME is not supported in this device/function.

26:26

RO

0x0

d2_support:

I/OxAPIC does not support power management state D2.

25:25

RO

0x0

d1_support:

I/OxAPIC does not support power management state D1.

24:22

RO

0x0

aux_current:

21:21

RO

0x0

device_specific_initialization:

20:20

RV

-

Reserved. 

19:19

RO

0x0

pme_clock:

This field is hardwired to 0h as it does not apply to PCI Express.

18:16

RWS_O

0x3

version:

This field is set to 3h (PM 1.2 compliant) as version number. Bit is RW_O to 

make the version 2h incase legacy OSes have any issues.

15:8

RO

0x0

next_capability_pointer:

This is the last capability in the chain and hence set to 0.

7:0

RO

0x1

capability_id:

Provides the PM capability ID assigned by PCI-SIG.

31:24

RO

0x0

data:

Not relevant for I/OxAPIC