Intel E7-8891 v2 CM8063601377422 사용자 설명서

340

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

Intel® Quick Data DMA Priority Register.

The Channel Control register controls the behavior of the DMA channel when specific 
events occur such as completion or errors.

7:0

RO

0x0

not_used:

15:10

RV

-

Reserved. 

9:9

RW_L

0x0

cmpwr_dca_enable:

When this bit is set, and the DMA engine supports DCA, then completion 

writes will be directed to the CPU indicated in Target CPU.This field is RW if 

CHANCNT register is 1 otherwise this register is RO.

8:8

RW_LV

0x0

in_use:

In Use. This bit indicates whether the DMA channel is in use. The first time 

this bit is read after it has been cleared, it will return 0 and automatically 

transition from 0 to 1, reserving the channel for the first consumer that reads 

this register. All subsequent reads will return 1 indicating that the channel is 

in use. This bit is cleared by writing a 0 value, thus releasing the channel. A 

consumer uses this mechanism to atomically claim exclusive ownership of 

the DMA channel. This should be done before attempting to program any 

register in the DMA channel register set. This field is RW if CHANCNT register 

is 1 otherwise this register is RO.

7:6

RV

-

Reserved. 

5:5

RW_L

0x0

desc_addr_snp_ctrl:

Descriptor address snoop control. 
1: When set, this bit indicates that the descriptors are not in coherent space 

and should not be snooped.
0: When cleared, the descriptors are in coherent space and each descriptor 

address must be snooped on Intel

®

QPI.

This field is RW if CHANCNT register is 1 otherwise this register is RO.

4:4

RW_L

0x0

err_int_en:

Error Interrupt Enable. This bit enables the DMA channel to generate an 

interrupt (MSI or legacy) when an error occurs during the DMA transfer. If 

Any Error Abort Enable (see below) is not set, then unaffiliated errors do not 

cause an interrupt.This field is RW if CHANCNT register is 1 otherwise this 

register is RO.