Intel E7-8891 v2 CM8063601377422 사용자 설명서

424

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

15:15

RO

0x0

detected_parity_error:

This bit is set when the device receives a packet on the primary side with an 

uncorrectable data error (including a packet with poison bit set) or an 

uncorrectable address/control parity error. The setting of this bit is 

regardless of the Parity Error Response bit (PERRE) in the PCICMD register. 

R2PCIe will never set this bit.

14:14

RO

0x0

signaled_system_error:

Hardwired to 0

13:13

RO

0x0

received_master_abort:

Hardwired to 0

12:12

RO

0x0

received_target_abort:

Hardwired to 0

11:11

RO

0x0

signaled_target_abort:

Hardwired to 0

10:9

RO

0x0

devsel_timing:

Not applicable to PCI Express. Hardwired to 0.

8:8

RO

0x0

master_data_parity_error:

Hardwired to 0

7:7

RO

0x0

fast_back_to_back:

Not applicable to PCI Express. Hardwired to 0.

6:6

RV

-

Reserved. 

5:5

RO

0x0

pci66mhz_capable:

Not applicable to PCI Express. Hardwired to 0.

4:4

RO

0x1

capabilities_list:

This bit indicates the presence of a capabilities list structure

3:3

RO

0x0

intx_status:

Hardwired to 0

2:0

RV

-

Reserved.