Intel E7-8870 v2 CM8063601272006 사용자 설명서
제품 코드
CM8063601272006
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
239
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.56 LNKCAP2
PCI Express Link Capabilities 2.
4:4
RW_V (Device 2 and 3
Function 0)
RW (Device 0
Function0, Device 2
and 3 Function 1-3)
0x0
0x1 (Device 0
Function 0)
compltodis:
Completion Timeout Disable
When set to 1b, this bit disables the Completion Timeout
When set to 1b, this bit disables the Completion Timeout
mechanism for all NP tx that IIO issues on the PCIe/DMI
link.
When 0b, completion timeout is enabled. Software can
When 0b, completion timeout is enabled. Software can
change this field while there is active traffic in the
root/DMI port.
3:0
RW_V (Device 2 and 3
Function 0)
RW (Device 0
Function0, Device 2
and 3 Function 1-3)
0x0
compltoval:
Completion Timeout Value on NP Tx that IIO issues on
PCIe/DMI
In Devices that support Completion Timeout
In Devices that support Completion Timeout
programmability, this field allows system software to
modify the Completion Timeout range. The following
encodings and corresponding timeout ranges are defined:
0000b = 10 ms to 50 ms
0001b = Reserved (IIO aliases to 0000b)
0010b = Reserved (IIO aliases to 0000b)
0101b = 16 ms to 55 ms
0110b = 65 ms to 210 ms
1001b = 260 ms to 900 ms
1010b = 1 s to 3.5 s
1101b = 4 s to 13 s
1110b = 17 s to 64 s
When software selects 17 s to 64 s range, CTOCTRL
0000b = 10 ms to 50 ms
0001b = Reserved (IIO aliases to 0000b)
0010b = Reserved (IIO aliases to 0000b)
0101b = 16 ms to 55 ms
0110b = 65 ms to 210 ms
1001b = 260 ms to 900 ms
1010b = 1 s to 3.5 s
1101b = 4 s to 13 s
1110b = 17 s to 64 s
When software selects 17 s to 64 s range, CTOCTRL
further controls the timeout value within that range. For
all other ranges selected by OS, the timeout value within
that range is fixed in IIO hardware.
Software can change this field while there is active traffic
Software can change this field while there is active traffic
in the root port.
This value will also be used to control PME_TO_ACK
This value will also be used to control PME_TO_ACK
Timeout. That is this field sets the timeout value for
receiving a PME_TO_ACK message after a PME_TURN_OFF
message has been transmitted. The PME_TO_ACK Timeout
has meaning only if bit 6 of MISCCTRLSTS register is set
to a 1b.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (DMI2 Mode)
Offset: 0xf8
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xb8
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xbc
Bit
Attr
Default
Description
31:8
RV
-
Reserved.