Fujifilm Xeon 5110 1.60GHz S26361-F3322-L160 데이터 시트
제품 코드
S26361-F3322-L160
Dual-Core Intel
®
Xeon
®
Processor 5100 Series Datasheet
111
Debug Tools Specifications
9
Debug Tools Specifications
Please refer to the Debug Port Design Guide for UP/DP Systems and the appropriate
platform design guidelines for information regarding debug tool specifications.
platform design guidelines for information regarding debug tool specifications.
provides collateral details.
9.1
Debug Port System Requirements
The Dual-Core Intel
®
Xeon
®
Processor 5100 Series debug port is the command and
control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time
control of the processors for system debug. The debug port, which is connected to the
FSB, is a combination of the system, JTAG and execution signals. There are several
mechanical, electrical and functional constraints on the debug port that must be
followed. The mechanical constraint requires the debug port connector to be installed in
the system with adequate physical clearance. Electrical constraints exist due to the
mixed high and low speed signals of the debug port for the processor. While the JTAG
signals operate at a maximum of 75 MHz, the execution signals operate at the common
clock FSB frequency. The functional constraint requires the debug port to use the JTAG
system via a handshake and multiplexing scheme.
control of the processors for system debug. The debug port, which is connected to the
FSB, is a combination of the system, JTAG and execution signals. There are several
mechanical, electrical and functional constraints on the debug port that must be
followed. The mechanical constraint requires the debug port connector to be installed in
the system with adequate physical clearance. Electrical constraints exist due to the
mixed high and low speed signals of the debug port for the processor. While the JTAG
signals operate at a maximum of 75 MHz, the execution signals operate at the common
clock FSB frequency. The functional constraint requires the debug port to use the JTAG
system via a handshake and multiplexing scheme.
In general, the information in this chapter may be used as a basis for including all run-
control tools in Dual-Core Intel
control tools in Dual-Core Intel
®
Xeon
®
Processor 5100 Series based system designs
including tools from vendors other than Intel.
Note:
The debug port and JTAG signal chain must be designed into the processor board to
utilize the XDP for debug purposes except for interposer solutions.
9.2
Target System Implementation
9.2.1
System Implementation
Specific connectivity and layout guidelines for the Debug Port are provided in the
Debug Port Design Guide for UP/DP Systems and the appropriate platform design
guidelines.
Debug Port Design Guide for UP/DP Systems and the appropriate platform design
guidelines.
9.3
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces
(LAIs) for use in debugging Dual-Core Intel
(LAIs) for use in debugging Dual-Core Intel
®
Xeon
®
Processor 5100 Series systems.
Tektronix and Agilent should be contacted to obtain specific information about their
logic analyzer interfaces. The following information is general in nature. Specific
information must be obtained from the logic analyzer vendor.
logic analyzer interfaces. The following information is general in nature. Specific
information must be obtained from the logic analyzer vendor.
Due to the complexity of Dual-Core Intel
®
Xeon
®
Processor 5100 Series based
multiprocessor systems, the LAI is critical in providing the ability to probe and capture
FSB signals. There are two sets of considerations to keep in mind when designing a
Dual-Core Intel
FSB signals. There are two sets of considerations to keep in mind when designing a
Dual-Core Intel
®
Xeon
®
Processor 5100 Series based system that can make use of an
LAI: mechanical and electrical.