Fujifilm Xeon 5110 1.60GHz S26361-F3322-L160 데이터 시트

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S26361-F3322-L160
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Dual-Core Intel
® 
Xeon
® 
Processor 5100 Series Datasheet
83
Thermal Specifications
When the Thermal Monitor is enabled, and a high temperature situation exists (that is, 
TCC is active), the clocks will be modulated by alternately turning the clocks off and on 
at a duty cycle specific to the processor (typically 30 - 50%). Cycle times are processor 
speed dependent and will decrease as processor core frequencies increase. A small 
amount of hysteresis has been included to prevent rapid active/inactive transitions of 
the TCC when the processor temperature is near its maximum operating temperature. 
Once the temperature has dropped below the maximum operating temperature, and 
the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.
With a thermal solution designed to meet Thermal Profile A, it is anticipated that the 
TCC would only be activated for very short periods of time when running the most 
power intensive applications. The processor performance impact due to these brief 
periods of TCC activation is expected to be so minor that it would be immeasurable. A 
thermal solution that is designed to Thermal Profile B may cause a noticeable 
performance loss due to increased TCC activation. Thermal Solutions that exceed 
Thermal Profile B will exceed the maximum temperature specification and affect the 
long-term reliability of the processor. In addition, a thermal solution that is significantly 
under designed may not be capable of cooling the processor even when the TCC is 
active continuously. Refer to the Dual-Core Intel
® 
Xeon
® 
Processor 5100 Series  
Thermal/Mechanical Design Guidelines or information on designing a thermal solution.
For the Dual-Core Intel® Xeon® Processor LV 5138, it is anticipated that the TCC 
would only be activated for very short periods of time when running the most power 
intensive applications. The processor performance impact due to these brief periods of 
TCC activation is expected to be so minor that it would be immeasurable. Utilization of 
a thermal solution that exceeds the Short-Term Thermal Profile, or which operates at 
the Short-Term Thermal Profile for a duration longer than the specified limits, do not 
meet the processor’s thermal specifications and may result in permanent damage to 
the processor. In addition, a thermal solution that is significantly under designed may 
not be capable of cooling the processor even when the TCC is active continuously. Refer 
to the Dual-Core Intel® Xeon® Processor LV 5138 in Embedded Applications Thermal/ 
Mechanical Design Guide
line for information on designing a thermal solution." The duty 
cycle for the TCC, when activated by the Thermal Monitor, is factory configured and 
cannot be modified. The Thermal Monitor does not require any additional hardware, 
software drivers, or interrupt handling routines. Refer to the Dual-Core Intel® Xeon® 
Processor LV 5138 in Embedded Applications Thermal/Mechanical Design Guideline
 for 
information on designing a thermal solution. 
6.2.1.2
Enhanced Thermal Monitor (TM2)
The Dual-Core Intel
® 
Xeon
® 
Processor 5100 Series  adds supports for an Enhanced 
Thermal Monitor capability known as Thermal Monitor 2 (TM2). This mechanism 
provides an efficient means for limiting the processor temperature by reducing the 
power consumption within the processor. TM2 requires support for dynamic VID 
transitions in the platform.
When TM2 is enabled, and a high temperature situation is detected, the Thermal 
Control Circuit (TCC) will be activated for both processor cores. The TCC causes the 
processor to adjust its operating frequency (via the bus multiplier) and input voltage 
(via the VID signals). This combination of reduced frequency and VID results in a 
reduction to the processor power consumption.
A processor enabled for TM2 includes two operating points, each consisting of a specific 
operating frequency and voltage, which is identical for both processor cores. The first 
operating point represents the normal operating condition for the processor. Under this 
condition, the core-frequency-to-system-bus multiplier utilized by the processor is that 
contained in the CLOCK_FLEX_MAX MSR and the VID that is specified in