Fujifilm Xeon 5060 S26361-F3312-L320 데이터 시트
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S26361-F3312-L320
Dual-Core Intel
®
Xeon
®
Processor 5100 Series Datasheet
23
Electrical Specifications
Note:
The LL_ID[1:0] signals are used to select the correct loadline slope for the processor.
Note:
The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor and may be
used for future processor compatibility or for keying.
2.6
Reserved or Unused Signals
All Reserved signals must remain unconnected. Connection of these signals to V
CC
, V
TT
,
V
SS
, or to any other signal (including each other) can result in component malfunction
for a land listing of the
processor and the location of all Reserved signals.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active high inputs, should be connected through a
resistor to ground (V
appropriate signal level. Unused active high inputs, should be connected through a
resistor to ground (V
SS
). Unused outputs can be left unconnected; however, this may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. Resistor values should be within ± 20% of the impedance of the baseboard
trace for FSB signals, unless otherwise noticed in the appropriate platform design
guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (R
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. Resistor values should be within ± 20% of the impedance of the baseboard
trace for FSB signals, unless otherwise noticed in the appropriate platform design
guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (R
TT
).
Some TAP, CMOS Asynchronous inputs and CMOS Asynchronous outputs do not include
on-die termination. Inputs and utilized outputs must be terminated on the baseboard.
Unused outputs may be terminated on the baseboard or left unconnected. Note that
leaving unused outputs unterminated may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing. Signal termination for
these signal types is discussed in the appropriate platform design guidelines.
on-die termination. Inputs and utilized outputs must be terminated on the baseboard.
Unused outputs may be terminated on the baseboard or left unconnected. Note that
leaving unused outputs unterminated may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing. Signal termination for
these signal types is discussed in the appropriate platform design guidelines.
Each of the TESTHI signals must be tied to the processor V
TT
individually using a
matched resistor, where a matched resistor has a resistance value within ± 20% of the
impedance of the board transmission line traces. For example, if the trace impedance is
50 Ω, then a value between 40 Ω and 60 Ω is required.
impedance of the board transmission line traces. For example, if the trace impedance is
50 Ω, then a value between 40 Ω and 60 Ω is required.
Table 2-5.
Loadline Selection Truth Table for LL_ID[1:0]
LL_ID1
LL_ID0
Description
0
0
Reserved
0
1
Dual-Core Intel
®
Xeon
®
Processor 5100 Series
1
0
Reserved
1
1
Reserved
Table 2-6.
Market Segment Selection Truth Table for MS_ID[1:0]
MS_ID1
MS_ID0
Description
0
0
Reserved
0
1
Dual-Core Intel
®
Xeon
®
Processor 5100 Series
1
0
Reserved
1
1
Reserved