Fujifilm Xeon S26361-F3099-L828 데이터 시트
제품 코드
S26361-F3099-L828
Datasheet
25
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on silicon
characterization, however they may be updated as further data becomes available. Listed frequencies are not necessarily
committed production frequencies.
committed production frequencies.
2. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at the manufacturing and
cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same
frequency might have different settings within the VID range. Please note that this differs from the VID employed by the
processor during power management event.
frequency might have different settings within the VID range. Please note that this differs from the VID employed by the
processor during power management event.
3. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is
required. See
for more information.
4. The voltage specification requirements are measured across vias on the platform for the VCCSENSE and VSSSENSE pins
close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M
Ω
minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system
is not coupled in the scope probe.
is not coupled in the scope probe.
and corresponding
. The processor should not be subjected to any static V
CC
level that exceeds the
V
CC_MAX
associated with any particular current. Failure to adhere to this specification can shorten processor lifetime.
6. Minimum V
CC
and maximum I
CC
are specified at the maximum processor case temperature (T
CASE
.
I
CC_MAX
is specified at the relative V
CC_MAX
point on the V
CC
load line. The processor is capable of drawing I
CC_MAX
for up to
7. V
TT
must be provided via a separate voltage source and must not be connected to V
CC
. This specification is measured at the
pin.
8. Baseboard bandwidth is limited to 20 MHz.
9. This specification refers to a single processor with R
9. This specification refers to a single processor with R
TT
enabled. Please note the end agent and middle agent may not require
I
TT
(max) simultaneously. This parameter is based on design characterization and not tested.
10.This specification refers to a single processor with R
TT
disabled. Please note the end agent and middle agent may not require
I
TT
(max) simultaneously. Details will be provided in future revisions of this document.
Table 9.
Voltage and Current Specifications
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
1
VID range
VID range for Low Voltage Intel
®
Xeon™ processor with 800 MHz
system bus
system bus
1.1125
1.2000
V
V
CC
V
CC
for Low Voltage Intel
®
Xeon™
processor with 800 MHz system bus
See
and
VID - I
CC
(max) * 1.25 m
Ω
V
V
TT
Front Side Bus termination voltage
(DC specification)
(DC specification)
1.176
1.20
1.224
V
Front Side Bus termination voltage
(AC & DC specification)
(AC & DC specification)
1.140
1.20
1.260
V
I
CC
I
CC
for Low Voltage Intel
®
Xeon™
processor with 800 MHz system bus
60
A
,
I
TT
Front Side Bus end-agent V
TT
current
4.8
A
I
TT
Front Side Bus mid-agent V
TT
current
1.5
A
I
CC_VCCA
I
CC
for PLL power pins
120
mA
I
CC_VCCIOPLL
I
CC
for PLL power pins
100
mA
I
CC_GTLREF
I
CC
for GTLREF pins
200
µA
I
SGNT
I
SLP
I
CC
Stop Grant for Low Voltage Intel
®
Xeon™ processor with 800 MHz
system bus
system bus
40
A
I
TCC
I
CC
TCC Active
I
CC
A
I
CC_TDC
I
CC
for Low Voltage Intel
®
Xeon™
processor with 800 MHz system bus
Thermal Design Current
Thermal Design Current
56
A