Fujifilm Xeon 5060 S26361-F3318-L320 데이터 시트
제품 코드
S26361-F3318-L320
Dual-Core Intel
®
Xeon
®
Processor 5100 Series Datasheet
19
Electrical Specifications
The processor core frequency is configured during reset by using values stored
internally during manufacturing. The stored value sets the highest bus fraction at which
the particular processor can operate. If lower speeds are desired, the appropriate ratio
can be configured via the CLOCK_FLEX_MAX MSR. For details of operation at core
frequencies lower than the maximum rated processor speed, refer to the Conroe and
Woodcrest Processor Family BIOS Writer’s Guide.
internally during manufacturing. The stored value sets the highest bus fraction at which
the particular processor can operate. If lower speeds are desired, the appropriate ratio
can be configured via the CLOCK_FLEX_MAX MSR. For details of operation at core
frequencies lower than the maximum rated processor speed, refer to the Conroe and
Woodcrest Processor Family BIOS Writer’s Guide.
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread
spectrum clocking. The Dual-Core Intel
(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread
spectrum clocking. The Dual-Core Intel
®
Xeon
®
Processor 5100 Series utilizes
differential clocks. Details regarding BCLK[1:0] driver specifications are provided in the
CK410B Clock Synthesizer/Driver Design Guidelines.
CK410B Clock Synthesizer/Driver Design Guidelines.
frequency to FSB multipliers and their corresponding core frequencies.
Notes:
1.
Listed frequencies illustrate clock frequency multipliers and are not necessarily committed production
frequencies for 40 W, 65 W or 80 W versions of Dual-Core Intel
®
Xeon
®
Processor 5100 Series.
2.
Individual processors operate only at or below the frequency marked on the package.
3.
For valid processor core frequencies, refer to the Dual-Core Intel
®
Xeon
®
Processor 5100 Series
Specification Update.
4.
The lowest bus ratio supported by the Dual-Core Intel
®
Xeon
®
Processor 5100 Seriesis 1/6.
2.4.1
Front Side Bus Frequency Select Signals (BSEL[2:0])
Upon power up, the FSB frequency is set to the maximum supported by the individual
processor. BSEL[2:0] are CMOS outputs which must be pulled up to V
processor. BSEL[2:0] are CMOS outputs which must be pulled up to V
TT
, and are used
for DC specifications.
defines the possible combinations of the signals and the frequency associated with each
combination. The frequency is determined by the processor(s), chipset, and clock
synthesizer. All FSB agents must operate at the same core and FSB frequency. See the
appropriate platform design guidelines for further details.
combination. The frequency is determined by the processor(s), chipset, and clock
synthesizer. All FSB agents must operate at the same core and FSB frequency. See the
appropriate platform design guidelines for further details.
Table 2-1.
Core Frequency to FSB Multiplier Configuration
Core Frequency to
FSB Multiplier
Core Frequency with
266 MHz FSB Clock
Processor
Notes
1/6
1.60 GHz
5110
1, 2, 3, 4
1/7
1.86 GHz
5120/5128
1, 2, 3
1/8
2.13 GHz
5138
1, 2, 3
Core Frequency to
FSB Multiplier
Core Frequency with
333 MHz FSB Clock
Processor
Notes
1/6
2.0 GHz
5130
1, 2, 3, 4
1/7
2.33 GHz
5140/5148
1, 2, 3
1/8
2.66 GHz
5150
1, 2, 3
1/9
3.0 GHz
5160
1, 2, 3
Table 2-2.
BSEL[2:0] Frequency Table (Sheet 1 of 2)
BSEL2
BSEL1
BSEL0
Bus Clock Frequency
0
0
0
266.666 MHz
0
0
1
Reserved
0
1
0
Reserved
0
1
1
Reserved
1
0
0
333.333 MHz