Fujifilm Xeon 5060 S26361-F3318-L320 데이터 시트

제품 코드

S26361-F3318-L320

Dual-Core Intel

Xeon

Processor 5100 Series Datasheet

Contents

Features......................................................................................................................9

Introduction............................................................................................................... 11
1.1

Terminology ..................................................................................................... 12

1.2

State of Data .................................................................................................... 14

1.3

References ....................................................................................................... 14

Electrical Specifications ............................................................................................... 17
2.1

Front Side Bus and GTLREF ................................................................................ 17

2.2

Power and Ground Lands.................................................................................... 17

2.3

Decoupling Guidelines........................................................................................ 18
2.3.1

VCC

Decoupling...................................................................................... 18

2.3.2

VTT

Decoupling ...................................................................................... 18

2.3.3

Front Side Bus AGTL+ Decoupling ............................................................ 18

2.4

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ....................................... 18
2.4.1

Front Side Bus Frequency Select Signals (BSEL[2:0]) .................................. 19

2.4.2

PLL Power Supply ................................................................................... 20

2.5

Voltage Identification (VID) ................................................................................ 20

2.6

Reserved or Unused Signals................................................................................ 23

2.7

Front Side Bus Signal Groups.............................................................................. 24

2.8

CMOS Asynchronous and Open Drain Asynchronous Signals .................................... 25

2.9

Test Access Port (TAP) Connection....................................................................... 25

2.10 Platform Environmental Control Interface (PECI) DC Specifications........................... 26

2.10.1 DC Characteristics .................................................................................. 26
2.10.2 Input Device Hysteresis .......................................................................... 27

2.11 Mixing Processors.............................................................................................. 27
2.12 Absolute Maximum and Minimum Ratings ............................................................. 27
2.13 Processor DC Specifications ................................................................................ 29

2.13.1 VCC Overshoot Specification .................................................................... 35
2.13.2 Die Voltage Validation ............................................................................. 36

Mechanical Specifications............................................................................................. 37
3.1

Package Mechanical Drawings ............................................................................. 37

3.2

Processor Component Keepout Zones................................................................... 41

3.3

Package Loading Specifications ........................................................................... 41

3.4

Package Handling Guidelines............................................................................... 42

3.5

Package Insertion Specifications.......................................................................... 42

3.6

Processor Mass Specifications ............................................................................. 42

3.7

Processor Materials............................................................................................ 43

3.8

Processor Land Coordinates ................................................................................ 43

Land Listing ............................................................................................................... 45
4.1

Dual-Core Intel

Xeon

Processor 5100 Series Pin Assignments ............................. 45

4.1.1

Land Listing by Land Name...................................................................... 45

4.1.2

Land Listing by Land Number ................................................................... 55

Signal Definitions ....................................................................................................... 65
5.1

Signal Definitions .............................................................................................. 65

Thermal Specifications ................................................................................................ 73
6.1

Package Thermal Specifications........................................................................... 73
6.1.1

Thermal Specifications ............................................................................ 73

6.1.2

Thermal Metrology ................................................................................. 81

6.2

Processor Thermal Features ................................................................................ 82
6.2.1

Thermal Monitor Features........................................................................ 82