Texas Instruments IC FLPT TMS320C28346ZFET PBGA-256 TID TMS320C28346ZFET 데이터 시트
제품 코드
TMS320C28346ZFET
GPIO
t
r(GPO)
t
f(GPO)
OSCCLK
SYSCLKOUT
Write to PLLCR
OSCCLK * 2
(Current CPU
Frequency)
OSCCLK/2
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, t
p
) is
2600 OSCCLK Cycles Long.)
OSCCLK * 4
(Changed CPU Frequency)
SPRS516D – MARCH 2009 – REVISED AUGUST 2012
shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0003 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0007 (setting for
OSCCLK x 8). Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase,
SYSCLKOUT = OSCCLK/2. After the PLL lock-up is complete (which takes 2600 OSCCLK cycles),
SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.
OSCCLK x 8). Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase,
SYSCLKOUT = OSCCLK/2. After the PLL lock-up is complete (which takes 2600 OSCCLK cycles),
SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.
Figure 6-7. Example of Effect of Writing Into PLLCR Register
6.10 General-Purpose Input/Output (GPIO)
6.10.1
GPIO - Output Timing
Table 6-11. General-Purpose Output Switching Characteristics
PARAMETER
MIN
MAX
UNIT
t
r(GPO)
Rise time, GPIO switching low to high
All GPIOs
11
ns
t
f(GPO)
Fall time, GPIO switching high to low
All GPIOs
11
ns
t
fGPO
Toggling frequency, GPO pins
40
MHz
Figure 6-8. General-Purpose Output Timing
122
Electrical Specifications
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