Texas Instruments IC FLPT TMS320C28346ZFET PBGA-256 TID TMS320C28346ZFET 데이터 시트
제품 코드
TMS320C28346ZFET
ePWM1/../9, HRPWM1/../9,
eCAP1/../6, eQEP1/../3
Peripheral
registers
Bridge
Clock enables
I/O
Peripheral
registers
Clock enables
I/O
eCAN-A/B
/4
Peripheral
registers
Clock enables
I/O
SPI-A/D, SCI-A/B/C
LOSPCP
LSPCLK
System
control
register
Bridge
SYSCLKOUT
Memorybus
C28x Core
GPIO
Mux
Clock enable
Peripheral
registers
I/O
McBSP-A/B
LOSPCP
LSPCLK
Clock enables
Bridge
HISPCP
DMA
bus
Bridge
ADC SOC
EXTSOC
DMA
Clock Enables
Peripheralbus
CPU timer
registers
CPU timer 0/1/2
Clock enable
Peripheral
registers
I2C-A
EXTADCCLK
SPRS516D – MARCH 2009 – REVISED AUGUST 2012
3.6
System Control
This section describes the oscillator, PLL and clocking mechanisms, the watchdog function and the low
power modes. shows the various clock and reset domains that will be discussed.
power modes. shows the various clock and reset domains that will be discussed.
Figure 3-8. Clock and Reset Domains
NOTE
There is a 2-SYSCLKOUT cycle delay from when the write to the PCLKCR0, PCLKCR1, and
PCLKCR2 registers (enables peripheral clocks) occurs to when the action is valid. This delay
must be taken into account before attempting to access the peripheral configuration
registers.
PCLKCR2 registers (enables peripheral clocks) occurs to when the action is valid. This delay
must be taken into account before attempting to access the peripheral configuration
registers.
Copyright © 2009–2012, Texas Instruments Incorporated
Functional Overview
53
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