Texas Instruments IC FLPT TMS320C28346ZFET PBGA-256 TID TMS320C28346ZFET 데이터 시트
제품 코드
TMS320C28346ZFET
INT1
to
INT12
INT14
28x
CPU
TINT2
TINT0
PIE
CPU-TIMER 0
CPU-TIMER 2
(Reserved for DSP/BIOS)
INT13
TINT1
CPU-TIMER 1
XINT13
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Reset
Timer Reload
SYSCLKOUT
TCR.4
(Timer Start Status)
TINT
16-Bit Timer Divide-Down
TDDRH:TDDR
32-Bit Timer Period
PRDH:PRD
32-Bit Counter
TIMH:TIM
16-Bit Prescale Counter
PSCH:PSC
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SPRS516D – MARCH 2009 – REVISED AUGUST 2012
4.2
32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
There are three 32-bit CPU-timers on the devices (CPU-Timer 0, CPU-Timer 1, CPU-Timer 2).
Timer 2 is reserved for DSP/BIOS™. CPU-Timer 0 and CPU-Timer 1 can be used in user applications.
These timers are different from the timers that are present in the ePWM modules.
These timers are different from the timers that are present in the ePWM modules.
NOTE
NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the
application.
application.
Figure 4-2. CPU-Timers
The timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in
A.
The timer registers are connected to the memory bus of the C28x processor.
B.
The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4-3. CPU-Timer Interrupt Signals and Output Signal
Copyright © 2009–2012, Texas Instruments Incorporated
Peripherals
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