Texas Instruments LM3431 Evaluation Board LM3431EVAL/NOPB LM3431EVAL/NOPB 데이터 시트
제품 코드
LM3431EVAL/NOPB
SNVS547G – NOVEMBER 2007 – REVISED MAY 2013
ELECTRICAL CHARACTERISTICS
Specifications in standard type are for T
J
= 25°C only, and limits in boldface type apply over the junction temperature (T
J
)
range of -40°C to +125°C. Unless otherwise stated, V
IN
= 12V. Minimum and Maximum limits are specified through test,
design, or statistical correlation. Typical values represent the most likely parametric norm at T
J
= 25°C, and are provided for
reference purposes only.
(1)
Parameter
Test Conditions
Min
Typ
Max
Units
SYSTEM
I
Q
Operating VIN Current
(2)
DIM = 5V
4.0
4.85
mA
I
Q_SB
Standby mode VIN current
EN = 1V
3.7
mA
I
Q_SD
Shutdown mode VIN Current
EN = 0V, Vin = 36V
15
23
µA
V
CC
VCC voltage
Iload = 25 mA, Vin = 5.5 to 36V
4.80
5
5.24
V
VCC
ILIM
VCC current limit
72
mA
UVLO
UVLO threshold
VIN rising, measured at VCC
4.36
4.50
V
hysteresis
0.28
V
V
EN_ST
Enable pin Standby threshold
EN rising
0.75
V
V
EN
Enable pin On threshold
EN rising
1.185
1.230
1.275
V
hysteresis
115
165
mV
LINEAR CURRENT CONTROLLER
V
REF
Reference Voltage
IREF < 300 µA
2.45
2.5
2.55
V
I
REFIN
REFIN input bias current
REFIN = 300 mV
14
80
nA
Δ
V
REF
/
Δ
V
IN
Line regulation
5.5V < VIN < 36V
0.000
%/V
1
V
NDRV
NDRVx drive voltage capability
INDRVx = 5 mA
3.7
V
I
NDRV_SK
NDRVx drive sink current
NDRV
X
= 0.9V
4
6
8
mA
I
NDRV_SC
NDRVx drive source current
NDRV
X
= 0.9V
10
15
20
mA
I
SNS
SNSx input bias current
SNSx = 300 mV
20
30
µA
V
OS
SNSx amp offset voltage
REFIN = 300 mV (LM3431)
-5
+5
mV
V
OS
SNSx amp offset voltage
REFIN = 300 mV (LM3431A)
-3
+3
mV
V
OS_DELTA
Ch. To Ch. offset voltage mismatch
(3)
REFIN = 300 mV, 25°C (LM3431)
5.5
mV
V
OS_DELTA
Ch. To Ch. offset voltage mismatch
(3)
REFIN = 300 mV, -40°C to +125°C
6
mV
(LM3431)
V
OS_DELTA
Ch. To Ch. offset voltage mismatch
(3)
REFIN = 300 mV, 25°C (LM3431A)
3.5
mV
V
OS_DELTA
Ch. To Ch. offset voltage mismatch
(3)
REFIN = 300 mV, -40°C to +125°C
4
mV
(LM3431A)
bw
SNSx amp bandwidth
At unity gain
2
MHz
V
LEDOFF
LEDOFF voltage
DIM low
5
V
V
DIM
DIM threshold
MODE/F > 4V
1.9
2.3
V
hysteresis
0.8
V
T
DIM
Minimum internal DIM pulse width
(4)
0.4
µs
DIM
DLY_R
DIM to NDRV delay time
DIM rising
100
ns
DIM
DLY_F
DIM to NDRV delay time
DIM falling
90
ns
TH
MODE/F
MODE/F threshold
For Digital Dimming control
3.8
V
I
MODE/F
MODE/F source/sink current
40
uA
V
MODE_L
MODE/F minimum voltage
Analog dimming mode
0.37
V
V
MODE_H
MODE/F peak voltage
Analog dimming mode
2.5
V
(1)
All room temperature limits are 100% production tested. All limits at temperature extremes are specified through correlation using
standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2)
IQ specifies the current into the VIN pin and applies to non-switching operation.
(3)
V
OS_DELTA
specifies the maximum absolute difference between the offset of any pair of SNS amplifiers.
(4)
The minimum DIM pulse width is an internal signal. Any pulse width may be applied to the DIM pin or generated via analog dimming
mode. A pulse width less than 0.4 µs will be internally extended to 0.4 µs.
mode. A pulse width less than 0.4 µs will be internally extended to 0.4 µs.
4
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