Cypress Semiconductor Cy8CKIT-050 Cy8CKIT-050B 사용자 설명서

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CY8CKIT-050 PSoC® 5LP Development Kit Guide, Doc. # 001-65816 Rev. *E

Port 5

16

P5[0]

Connected to 2 points:
1. Connected to CapSense slider segment
2. Connected to Pin 28 on Port D

17

P5[1]

Connected to 2 points:
1. Connected to CapSense slider segment
2. Connected to Pin 27 on Port D

18

P5[2]

Connected to 2 points:
1. Connected to CapSense slider segment
2. Connected to Pin 26 on Port D

19

P5[3]

Connected to 2 points:
1. Connected to CapSense slider segment
2. Connected to Pin 25 on Port D

31

P5[4]

Connected to 2 points:
1. Connected to CapSense slider segment
2. Connected to Pin 24 on Port D

32

P5[5]

Connected to 2 points:
1. Connected to CapSense button CSB1
2. Connected to Pin 23 on Port D

33

P5[6]

Connected to 2 points:
1. Connected to CapSense button CSB2
2. Connected to Pin 22 on Port D

34

P5[7]

Connected to Pin 21 on Port D

Port 6

89

P6[0]

Connected to Pin 5 on P9

90

P6[1]

Connected to SW2 push button

91

P6[2]

Connected to LED3

92

P6[3]

Connected to LED4

6

P6[4]

Connected to CapSense Modulation Capacitor CMOD

7

P6[5]

Connected to 2 points:
1. Connected to VR POT
2. Connected to Pin 5 on P6

8

P6[6]

Connected to Pin 6 on P9

9

P6[7]

Unused/No Connect

Port 12

53

P12[0]

Connected to Pin 34 (SCL) on  Port D and Port E

54

P12[1]

Connected to Pin 33 (SDA) on  Port D and Port E

67

P12[2]

Connected to Pin 32 on Port D and Port E

68

P12[3]

Connected to Pin 31 on Port D and Port E

4

P12[4]

Connected to Pin 1 on P9

5

P12[5]

Connected to Pin 2 on P9

29

P12[6]

Connected to Pin 3 on P9

30

P12[7]

Connected to Pin 4 on P9