Texas Instruments TPS60250-185 Evaluation Board TPS60250EVM-185 TPS60250EVM-185 데이터 시트
제품 코드
TPS60250EVM-185
SERIAL INTERFACE
Data line
stable;
data valid
DATA
CLK
Change
of data
allowed
START Condition
DATA
CLK
STOP Condition
S
P
CE
SLVS769C – APRIL 2007 – REVISED APRIL 2008
............................................................................................................................................................
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applications. In order to satisfy today's requirements on LED current , the TPS60250/2 cover the low LED current
area from 100
area from 100
µ
A to 1.5 mA with 100
µ
A dimming steps (total 16 steps for a 25 mA maximum current) for the
new LCD panels which have improved transparency rates. For LED currents in the range from 2 mA to 25 mA,
the devices use 48 dimming steps with 0.5 mA steps. Also, DM5 has 4 dimming steps once the current path is
assigned for auxiliary applications with a 80 mA maximum current.
the devices use 48 dimming steps with 0.5 mA steps. Also, DM5 has 4 dimming steps once the current path is
assigned for auxiliary applications with a 80 mA maximum current.
The serial interface is compatible with the standard and fast mode I
2
C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the WLED driver solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements. Register contents remain intact as long as
V
new values depending on the instantaneous application requirements. Register contents remain intact as long as
V
CC
remains above UVLO2 (typical 1.3 V).
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS60250/2 devices generate an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS60250/2 devices must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. Setup and hold times must be taken into account. During read operations, a master
must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked
out of the slave. In this case, the slave TPS60250/2 devices must leave the data line high to enable the master
to generate the stop condition.
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS60250/2 devices generate an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS60250/2 devices must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. Setup and hold times must be taken into account. During read operations, a master
must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked
out of the slave. In this case, the slave TPS60250/2 devices must leave the data line high to enable the master
to generate the stop condition.
Figure 15. Bit Transfer on the Serial Interface
Figure 16. START and STOP Conditions
12
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