Texas Instruments SN65CML100 Evaluation Module SN65CML100EVM SN65CML100EVM 데이터 시트

3-4

9

Copper Foil CH A1

Copper Foil CH A1

.0062 PREPREG

.0062 PREPREG

CORE .015 C1/0 A1
.0122 PREPREG
CORE .015 C0/1 A1

SECTION A - A

NO SCALE

TOP SIDE-SIGNAL/GND FILL (LAYER 1)

INT1-GND PLANE (LAYER 2)

INT2-VCC SPLIT PLANE (LAYER 3)

9

BOTTOM SIDE-GND PLANE (LAYER 4)

Symbol

 
 
 

Diameter (in)

0.0160
0.0320
0.0400
0.0500
0.1250
0.2720

Plated

Yes
Yes
Yes
Yes
Yes
Yes

Quantity

49

8
2
3
4
3

Through Holes

3.000

A

A

3.000

DATUM 0,0

TOP SIDE SHOWN

DRILL

0.250

0.250

N

N

THIS IS AN IMPEDANCE CONTROLLED BOARD.

GENERAL NOTES: UNLESS OTHERWISE SPECIFIED

1. ALL FABRICATION ITEMS MUST MEET OR EXCEED BEST

INDUSTRY PRACTICE. IPC-A 600C ( Commercial Std.)

2.LAMINATE MATERIAL: NELCO N4000-13 (DO NOT USE - 13SI)
3. COOPER WEIGHT:1 OZ. START INTERNAL AND 1/2 OZ. START EXTERNAL
4. FINISHED BOARD THICKNESS: .062 

±

10%

5. MAXIMUM WARP AND TWIST TO BE .005 INCH PER INCH
6 MINIMUM COPPER WALL THICKNESS OF PLATED-THRU

HOLES TO BE .001 INCH

7 MINIMUM ANNULAR RING OF PLATED-THRU

HOLES TO BE .002 INCH

8. MINIMUM ALLOWABLE LINE REDUCTION TO BE

20% OR .002 WHICHEVER IS GREATER

9. 0.013 INCH SIGNAL LINES ON LAYER 1 TO BE

IMPEDANCE CONTROLLED 50 OHMS TO GND 

±

10%

0.010 INCH SIGNAL LINES ON LAYER 1 TO BE
IMPEDANCE CONTROLLED 100 OHMS TO EACH OTHER 

±

10%

10. DIELECTRIC CONSTANTS ARE:

     CORE: 3.2
PREPREG:3.2

PROCESS NOTES:

1. CIRCUITRY ON OUTER LAYERS TO BE PLATED WITH TIN LEAD
2. SOLDERMASK BOTH SIDES PER ARTWORK: GREEN LPI
3. SILKSCREEN BOTH SIDE PER ARTWORK: COLOR=WHITE

4

N

6434666A       PWA, BENCH, EVALUATION BOARD, SN65LVDS100/101D, EVM            10/31/01