Texas Instruments LM3429 Evaluation Boards LM3429BSTEVAL/NOPB LM3429BSTEVAL/NOPB 데이터 시트
제품 코드
LM3429BSTEVAL/NOPB
1
Z
1
P
)
,
min(
Z
Z
5
x
0
U
T
2
P
=
Z
=
0
U
T
=
SNS
CSH
R
R
500V
D
x
x
x
c
620V
D
x
c
(
)
LIM
LED
R
I
D
1
x
x
+
(
)
LIM
HSP
R
R
D
1
x
x
+
=
0
U
T
=
SNS
CSH
R
R
500V
D
x
x
x
c
310V
D
x
c
LIM
LED
R
I
x
LIM
HSP
R
R
2
x
x
SNS
620V
R
R
500V
=
x
x
CSH
LIM
LED
R
I
x
0
U
T
=
LIM
HSP
R
R
x
=
D
r
2
D
c
x
1
Z
Z
L1
D x
=
D
r
2
D
c
x
1
Z
Z
L1
1
P
=
Z
1+D
O
D
C
r x
3
1
P
=
Z
2
O
D
C
r x
3
1
P
=
Z
1
O
D
C
r x
3
x
=
¨
¨
©
©
§
+
s
1
Z
1
P
¸
¸
¹
¹
·
0
U
T
U
T
¨
¨
©
©
§
-
s
1
Z
1
Z
¸
¸
¹
¹
·
SNVS616G – APRIL 2009 – REVISED MAY 2013
Boost and Buck-boost
(47)
Where the pole (
ω
P1
) is approximated:
Buck
(48)
Boost
(49)
Buck-boost
(50)
And the RHP zero (
ω
Z1
) is approximated:
Boost
(51)
Buck-boost
(52)
And the uncompensated DC loop gain (T
U0
) is approximated:
Buck
(53)
Boost
(54)
Buck-boost
(55)
For all topologies, the primary method of compensation is to place a low frequency dominant pole (
ω
P2
) which
will ensure that there is ample phase margin at the crossover frequency. This is accomplished by placing a
capacitor (C
capacitor (C
CMP
) from the COMP pin to GND, which is calculated according to the lower value of the pole and the
RHP zero of the system (shown as a minimizing function):
(56)
Copyright © 2009–2013, Texas Instruments Incorporated
27
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