Texas Instruments TPS61080/81-147 Evaluation Board TPS61080/81EVM-147 TPS61080EVM-147 TPS61080EVM-147 데이터 시트
제품 코드
TPS61080EVM-147
FSW
Vout
EN
GND
T
h
e
r
m
a
l
P
a
d
Cs
C1
R1
R2
C3*
C2
L1
Vin
R3*
PGND
SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013
During a load transient, the output capacitor at the output of the boost converter has to supply or absorb transient
current before the inductor current ramps up its steady state value. Larger capacitors always help to reduce the
voltage over and under shoot during a load transient. A larger capacitor also helps loop stability. Care must be
taken when evaluating a ceramic capacitor’s derating under dc bias, aging and AC signal. For example, larger
form factor capacitors (in 1206 size) have their self resonant frequencies in the range of the switching frequency.
So the effective capacitance is significantly lower. The Dc bias can also significantly reduce capacitance.
Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore, almost leave
margin on voltage rating to ensure adequate capacitance.
current before the inductor current ramps up its steady state value. Larger capacitors always help to reduce the
voltage over and under shoot during a load transient. A larger capacitor also helps loop stability. Care must be
taken when evaluating a ceramic capacitor’s derating under dc bias, aging and AC signal. For example, larger
form factor capacitors (in 1206 size) have their self resonant frequencies in the range of the switching frequency.
So the effective capacitance is significantly lower. The Dc bias can also significantly reduce capacitance.
Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore, almost leave
margin on voltage rating to ensure adequate capacitance.
The popular vendors for high value ceramic capacitors are:
TDK (
Murata (
LAYOUT CONSIDERATION
As for all switching power supplies, the layout is an important step in the design, especially for high current and
high switching frequencies. If layout is not carefully done, the regulator could show stability problems as well as
EMI problems. Therefore, use wide and short traces for high current paths and for power ground tracks. Input
capacitor needs not only close to the VIN, but also to the GND pin to reduce the voltage ripple seen by the IC.
The L and SW pin are conveniently located on the edge of the IC, therefore inductor can be placed close to the
IC. The output capacitor needs to be placed near the load to minimize ripple and maximize transient
performance.
high switching frequencies. If layout is not carefully done, the regulator could show stability problems as well as
EMI problems. Therefore, use wide and short traces for high current paths and for power ground tracks. Input
capacitor needs not only close to the VIN, but also to the GND pin to reduce the voltage ripple seen by the IC.
The L and SW pin are conveniently located on the edge of the IC, therefore inductor can be placed close to the
IC. The output capacitor needs to be placed near the load to minimize ripple and maximize transient
performance.
To minimize the effects of ground noise, use a common node for all power ground that is connected to the
PGND pin, and a different one for signal ground tying to the GND pin. Connect two ground nodes together at the
load if possible. This allows the GND pin to be close to the output ground for good DC regulation. Any voltage
difference between these two nodes would be gained up by feedback divider on the output. It is also beneficial to
have the ground of the output capacitor close to PGND since there is a large current between them. To lay out
signal ground, it is recommended to use short traces separated from power ground traces.
PGND pin, and a different one for signal ground tying to the GND pin. Connect two ground nodes together at the
load if possible. This allows the GND pin to be close to the output ground for good DC regulation. Any voltage
difference between these two nodes would be gained up by feedback divider on the output. It is also beneficial to
have the ground of the output capacitor close to PGND since there is a large current between them. To lay out
signal ground, it is recommended to use short traces separated from power ground traces.
16
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: