Texas Instruments CDCE421AEVM - CDCE421A Evalution Module CDCE421AEVM CDCE421AEVM 데이터 시트
제품 코드
CDCE421AEVM
7.2
Configuration for Programming (with USB Cable Attached)
7.3
Configuration for Testing from a Saved Configuration (with USB Cable Removed after
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Schematics and Layout
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Schematics and Layout
The CDCE421AEVM can also use power supplied through the USB cable as its sole power source.
However, as mentioned earlier, because of power-supply variances in the USB supply, this configuration
is not recommended for measurements. This setup is helpful for saving configuration settings to the
CDCE421A and then later powering the device from its internal memory (a useful option if there is no USB
port available on a PC in a lab or test chamber). In this configuration, JP1 must be moved from its default
position to the new position shown in
However, as mentioned earlier, because of power-supply variances in the USB supply, this configuration
is not recommended for measurements. This setup is helpful for saving configuration settings to the
CDCE421A and then later powering the device from its internal memory (a useful option if there is no USB
port available on a PC in a lab or test chamber). In this configuration, JP1 must be moved from its default
position to the new position shown in
. Additionally, the Enable (onboard) Power box must be
checked on the GUI software, followed by pushing the Apply software button.
Figure 8. JP1 Settings
Programming)
When operating the CDCE421A without the USB programming cable, the CDCE421AEVM must be
pre-programmed in one of the configurations discussed in this section and then reconfigured for external
power-supply usage.
pre-programmed in one of the configurations discussed in this section and then reconfigured for external
power-supply usage.
Before making these board modifications, the CDCE421A settings must be saved with one of the above
USB cable attached configurations. Use the Write Chronos Settings to EEPROM NO LOCKING software
button to save the CDCE421A settings to the device-internal EEPROM. After the settings are saved to the
EEPROM, the USB cable can be removed. Once the cable has been disconnected, jumper JP1 should be
in the Using External 3.3-V Supply position (as shown in
USB cable attached configurations. Use the Write Chronos Settings to EEPROM NO LOCKING software
button to save the CDCE421A settings to the device-internal EEPROM. After the settings are saved to the
EEPROM, the USB cable can be removed. Once the cable has been disconnected, jumper JP1 should be
in the Using External 3.3-V Supply position (as shown in
). The EVM is now ready for use without
the USB cable connected. The CDCE421A will always start from its saved configuration state in this
mode.
mode.
If the CDCE421A must be isolated from the microcontroller, the switch that corresponds to the block in
use should be set to Off for CE_x, SDATA_x, and LVPECL_TERM_x (where x represents the block
name). The power line switch for that block, however, should be kept on. This sequence also allows for
the USB cable to be removed without affecting performance while the CDCE421A is powered up.
use should be set to Off for CE_x, SDATA_x, and LVPECL_TERM_x (where x represents the block
name). The power line switch for that block, however, should be kept on. This sequence also allows for
the USB cable to be removed without affecting performance while the CDCE421A is powered up.
through
show the printed circuit board (PCB) schematics for the CDCE421AEVM.
Note:
Board layouts are not to scale. These figures are intended to show how the board is laid out;
they are not intended to be used for manufacturing CDCE421AEVM PCBs.
they are not intended to be used for manufacturing CDCE421AEVM PCBs.
SCAU031 – June 2009
10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board
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