Texas Instruments CDCE421AEVM - CDCE421A Evalution Module CDCE421AEVM CDCE421AEVM 데이터 시트
제품 코드
CDCE421AEVM
1
General Description
2
Signal Path and Control Circuitry
www.ti.com
General Description
The
is a high-performance, low phase noise clock generator. It has two fully integrated,
low-noise, LC-based voltage-controlled oscillators (VCOs) that operate in the range of 1.75 GHz to 2.35
GHz.
GHz.
The CDCE421A has an integrated crystal oscillator circuitry that operates in conjunction with an external
AT-cut crystal to produce a stable frequency reference for the PLL-based frequency synthesizer. A 3.3-V
LVCMOS level input can also be used instead of a crystal to provide a frequency reference to the PLL.
AT-cut crystal to produce a stable frequency reference for the PLL-based frequency synthesizer. A 3.3-V
LVCMOS level input can also be used instead of a crystal to provide a frequency reference to the PLL.
This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCE421A.
This fully assembled and factory-tested evaluation board allows complete validation of the CDCE421A
device functionalities. Throughout this document, the acronym EVM and the phrases evaluation module
and evaluation board are synonymous with the CDCE421AEVM.
This fully assembled and factory-tested evaluation board allows complete validation of the CDCE421A
device functionalities. Throughout this document, the acronym EVM and the phrases evaluation module
and evaluation board are synonymous with the CDCE421AEVM.
illustrates the CDCE421AEVM.
For optimum performance, the board is equipped with 50-
Ω
SMA connectors and well-controlled, 50-
Ω
impedance microstrip transmission lines.
The CDCE421A can accept a 29-MHz to 44-MHz frequency input from either an LVCMOS source (up to
3.3 V) or a crystal in the same frequency range.
3.3 V) or a crystal in the same frequency range.
The CDCE421AEVM is divided into four blocks. The programming section and device power for each
block can be enabled or disabled through individual switches provided for each block. For example, in
order to enable power and programming for Block A, the switch must be in the position shown in
block can be enabled or disabled through individual switches provided for each block. For example, in
order to enable power and programming for Block A, the switch must be in the position shown in
The other blocks are disabled with the respective switches as the figure illustrates.
For more information about the CDCE421A, see the
available for
download from the TI web site (
).
Figure 2. Enabled (Block A) and Disabled (Blocks B, C, D) Switch Positions
SCAU031 – June 2009
10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board
3