Texas Instruments THS5671A Evaluation Module THS5671EVM THS5671EVM 데이터 시트
제품 코드
THS5671EVM
EVM Operating Modes
1.2.2 Control/Interface
The control signals can be derived from either a DSK/microprocessor or from a dedicated GND and 3-V to
5-V supply connected to J3. The signals from either source are similar. The decision regarding which host
system to use is left to of the user.
5-V supply connected to J3. The signals from either source are similar. The decision regarding which host
system to use is left to of the user.
1.2.3 Output Stage
Several circuits for achieving a single-ended output from the DAC
’
s differential outputs are designed into
the THS56X1 EVM.
shows the arrangement of the output circuits.
1.3
EVM Operating Modes
There are two modes of operation for the EVM:
•
DSK/microprocessor mode
•
Pattern generator mode
Each of these modes is discussed below.
1.3.1 C542/C54xx DSK/Microprocessor Mode
The C542/C54XX starter kit (DSK)/microprocessor is used to supply the sample clock (CLKOUT), the
EVM device-select control signals, and data via the 16-bit parallel data bus. The digital data sent to the
DAC for conversion is usually stored in a lookup table
EVM device-select control signals, and data via the 16-bit parallel data bus. The digital data sent to the
DAC for conversion is usually stored in a lookup table
—
see the example program shown in Section 5. If
the input digital data source can conveniently provide data and sample-clock, then the user must connect
jumper W1 or make the following connections: J3 pin1 to J3 pin2, J2 pin 3 and pin 5 tied to either 3.3 V or
5 V in order to enable the SN74LVT245B buffers.
jumper W1 or make the following connections: J3 pin1 to J3 pin2, J2 pin 3 and pin 5 tied to either 3.3 V or
5 V in order to enable the SN74LVT245B buffers.
W5 is used to set the THS56X1A CommsDAC operating modes. Mode 0 ( W5, closed ) configures the
device for binary input data word format. Mode 1 ( W5, opened) sets a twos complement input data word
format.
device for binary input data word format. Mode 1 ( W5, opened) sets a twos complement input data word
format.
1.3.2 Pattern Generator Mode
A pattern generator, similar to the Tektronix HFS9009, can be used to supply the input digital data stream
and sample clock. The EVM device select signal is provided via J3 or W1. The pattern generator is
programmed, typically, to output a sine wave and the appropriate sample clock (either 100 MHz or 67
MHz). The clock feeds directly into SMA connector J5 and the digital data to J1 goes via a SMA-to-ribbon
cable adapter (see
and sample clock. The EVM device select signal is provided via J3 or W1. The pattern generator is
programmed, typically, to output a sine wave and the appropriate sample clock (either 100 MHz or 67
MHz). The clock feeds directly into SMA connector J5 and the digital data to J1 goes via a SMA-to-ribbon
cable adapter (see
W5 is used to set the THS56X1A CommsDAC operating modes. Mode 0 ( W5, closed ) configures the
device for binary input data word format. Mode 1 ( W5, opened) sets a twos complement input data word
format.
device for binary input data word format. Mode 1 ( W5, opened) sets a twos complement input data word
format.
10
EVM Overview
SLAU032C
–
February 2001
–
Revised April 2011
Copyright
©
2001
–
2011, Texas Instruments Incorporated