Texas Instruments TLV320AIC3104 Evaluation Module (EVM) and USB motherboard TLV320AIC3104EVM-K TLV320AIC3104EVM-K 데이터 시트
제품 코드
TLV320AIC3104EVM-K
BCLK
WCLK
0
0
T0152-01
1/fs
LSB
LSB
LSB MSB
MSB
Left Channel
Right Channel
1
1
2
2
SDIN/SDOUT
n–1
n–1
n–1
n–2
n–3
n–3
n–4
n–2
BCLK
WCLK
1
1
0
0
T0151-01
1/fs
LSB
MSB
Left Channel
Right Channel
2
2
SDIN/SDOUT
n–1
n–1
n–1
1 Clock Before MSB
n–2
n–2
n–3
n–3
SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010
I
2
S MODE
In I
2
S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock.
the rising edge of the word clock.
Figure 20. I
2
S Serial Data Bus Mode Operation
DSP MODE
In DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first,
immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.
immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.
Figure 21. DSP Serial Data Bus Mode Operation
Copyright © 2007–2010, Texas Instruments Incorporated
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