Texas Instruments TLV320AIC3104 Evaluation Module (EVM) and USB motherboard TLV320AIC3104EVM-K TLV320AIC3104EVM-K 데이터 시트
제품 코드
TLV320AIC3104EVM-K
SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010
Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It
can be varied from 7 ms to 1,408 ms. The extended right-channel attack time can be programmed by writing to
page 0, register 103, and the left channel is programmed by writing to page 0, register 105.
can be varied from 7 ms to 1,408 ms. The extended right-channel attack time can be programmed by writing to
page 0, register 103, and the left channel is programmed by writing to page 0, register 105.
Decay time determines how quickly the PGA gain is increased when the input signal is too low. It can be varied
in the range from 0.05 s to 22.4 s. The extended right-channel decay time can be programmed by writing to page
0, register 104, and the left channel is programmed by writing to page 0, register 106.
in the range from 0.05 s to 22.4 s. The extended right-channel decay time can be programmed by writing to page
0, register 104, and the left channel is programmed by writing to page 0, register 106.
The actual AGC decay time maximum is based on a counter length, so the maximum decay time scales with the
clock setup that is used.
clock setup that is used.
shows the relationship of the NCODEC ratio to the maximum time available for
the AGC decay. In practice, these maximum times are extremely long for audio applications and should not limit
any practical AGC decay time that is needed by the system.
any practical AGC decay time that is needed by the system.
Table 4. AGC Decay Time Restriction
NCODEC RATIO
MAXIMUM DECAY TIME (SECONDS)
1
4
1.5
5.6
2
8
2.5
9.6
3
11.2
3.5
11.2
4
16
4.5
16
5
19.2
5.5
22.4
6
22.4
Noise gate threshold determines the level below which if the input speech average value falls, AGC considers it
as a silence and hence brings down the gain to 0 dB in steps of 0.5 dB every sample period and sets the noise
threshold flag. The gain stays at 0 dB unless the input speech signal average rises above the noise threshold
setting. This ensures that noise does not get gained up in the absence of speech. Noise threshold level in the
AGC algorithm is programmable from –30 dB to –90 dB relative to full scale. A disable noise gate feature is also
available. This operation includes programmable debounce and hysteresis functionality to avoid the AGC gain
from cycling between high gain and 0 dB when signals are near the noise threshold level. When the noise
threshold flag is set, the status of gain applied by the AGC and the saturation flag should be ignored.
as a silence and hence brings down the gain to 0 dB in steps of 0.5 dB every sample period and sets the noise
threshold flag. The gain stays at 0 dB unless the input speech signal average rises above the noise threshold
setting. This ensures that noise does not get gained up in the absence of speech. Noise threshold level in the
AGC algorithm is programmable from –30 dB to –90 dB relative to full scale. A disable noise gate feature is also
available. This operation includes programmable debounce and hysteresis functionality to avoid the AGC gain
from cycling between high gain and 0 dB when signals are near the noise threshold level. When the noise
threshold flag is set, the status of gain applied by the AGC and the saturation flag should be ignored.
Maximum PGA gain applicable allows the user to restrict the maximum PGA gain that can be applied by the
AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than
programmed noise threshold. It can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB.
AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than
programmed noise threshold. It can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB.
30
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