Texas Instruments THS7303EVM Evaluation Module THS7303EVM THS7303EVM 데이터 시트
제품 코드
THS7303EVM
Input
Pin
Input
Internal
Circuitry
Level
Shifter
V
S+
SLOS479B
–
OCTOBER 2005
–
REVISED MARCH 2011
INPUT MODES OF OPERATION: DC + 135-mV SHIFT
Clipping occurs with a 0-V applied input signal when the input mode is set to dc. The clipping can reduce the
sync amplitudes (both horizontal and vertical sync amplitudes) on the video signal. A problem occurs if the
receiver of this video signal uses an AGC loop to account for losses in the transmission line. Some video AGC
circuits derive gain from the horizontal sync amplitude. If clipping occurs on the sync amplitude, then the AGC
circuit can increase the gain too much, resulting in too much luma and/or chroma amplitude gain correction. This
may result in a picture with an overly bright display with too much color saturation.
sync amplitudes (both horizontal and vertical sync amplitudes) on the video signal. A problem occurs if the
receiver of this video signal uses an AGC loop to account for losses in the transmission line. Some video AGC
circuits derive gain from the horizontal sync amplitude. If clipping occurs on the sync amplitude, then the AGC
circuit can increase the gain too much, resulting in too much luma and/or chroma amplitude gain correction. This
may result in a picture with an overly bright display with too much color saturation.
Other AGC circuits use the chroma burst amplitude for amplitude control, and a reduction in the sync signals
does not alter the proper gain setting. It is good engineering design practice to ensure saturation/clipping does
not take place. Transistors always take a finite amount of time to come out of saturation. This saturation could
possibly result in timing delays or other aberrations on the signals.
does not alter the proper gain setting. It is good engineering design practice to ensure saturation/clipping does
not take place. Transistors always take a finite amount of time to come out of saturation. This saturation could
possibly result in timing delays or other aberrations on the signals.
To eliminate saturation/clipping problems, the THS7303 has a dc + 135 mV shift input mode. This mode takes
the input voltage and adds an internal +135 mV shift to the signal. Since the THS7303 also has a gain of 6 dB (2
V/V), the resulting output with a 0-V applied input signal is about 270 mV. The THS7303 rail-to-rail output stage
can create this level while connected to a typical video load. This ensures that no saturation/clipping of the sync
signals occurs. This is a constant shift regardless of the input signal. For example, if a 1-V input is applied, the
output is at 2.27 V.
the input voltage and adds an internal +135 mV shift to the signal. Since the THS7303 also has a gain of 6 dB (2
V/V), the resulting output with a 0-V applied input signal is about 270 mV. The THS7303 rail-to-rail output stage
can create this level while connected to a typical video load. This ensures that no saturation/clipping of the sync
signals occurs. This is a constant shift regardless of the input signal. For example, if a 1-V input is applied, the
output is at 2.27 V.
As with the dc-input mode, the input impedance of the THS7303 is
>
1 M
Ω
. Additionally, the same input bias
current of about 0.6
μ
A appears at the input. Following the same precautions as stipulated with the dc-input
mode of operation minimizes any potential issues.
shows the equivalent input circuit while in the dc +
135 mV shift mode of operation. Note that the internal voltage shift does not appear at the input pin, only the
output pin.
output pin.
Figure 61. Equivalent DC + 135 mV Input Mode Circuit
Copyright
©
2005
–
2011, Texas Instruments Incorporated
25
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