Texas Instruments THS7303EVM Evaluation Module THS7303EVM THS7303EVM 데이터 시트
제품 코드
THS7303EVM
SLOS479B
–
OCTOBER 2005
–
REVISED MARCH 2011
EXAMPLE: WRITING TO THE THS7303
To initiate a write operation to the THS7303, an I
2
C master generates a start condition (S) followed by the
THS7303 I
2
C address (as shown below) in MSB first bit order, followed by a '0' to indicate a write cycle. After
receiving an acknowledge from the THS7303, the master presents the sub-address (channel) it wants to write
consisting of one byte of data, MSB first. The THS7303 acknowledges the byte after completion of the transfer.
Finally the master presents the data it wants to write to the register (channel) and the THS7303 acknowledges
the byte. The I
consisting of one byte of data, MSB first. The THS7303 acknowledges the byte after completion of the transfer.
Finally the master presents the data it wants to write to the register (channel) and the THS7303 acknowledges
the byte. The I
2
C master then terminates the write operation by generating a stop condition (P). Note that the
THS7303 does not support multi-byte transfers. To write to all three channels (or registers), this procedure must
be repeated for each register, one series at a time (that is, repeat steps 1 through 8 for each channel).
be repeated for each register, one series at a time (that is, repeat steps 1 through 8 for each channel).
Example of THS7303 Write Operation:
Step 1
0
I
2
C Start (Master)
S
Step 2
7
6
5
4
3
2
1
0
I
2
C General Address (Master)
0
1
0
1
1
X
X
0
Where each X logic state is defined by I
2
C A1 and I
2
C A0 pins being tied to either V
S+
or GND.
Step 3
9
I
2
C Acknowledge (Slave)
A
Step 4
7
6
5
4
3
2
1
0
I
2
C Write Channel Address (Master)
0
0
0
0
0
0
Addr
Addr
Where Addr is determined by the values shown in
Step 5
9
I
2
C Acknowledge (Slave)
A
Step 6
7
6
5
4
3
2
1
0
I
2
C Write Data (Master)
Data
Data
Data
Data
Data
Data
Data
Data
Where Data is determined by the values shown in
Step 7
9
I
2
C Acknowledge (Slave)
A
Step 8
0
I
2
C Stop (Master)
P
For Step 6, an example of the proper bit control for selecting Input B of the MUX, a 720p Y
’
channel signal with
ac STC lowest line tilt and with the shortest sync filter is 1111 0101.
For Step 7, the ACK state means the THS7303 pulls the SDA line low until the next cycle on the SCL line.
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Copyright
©
2005
–
2011, Texas Instruments Incorporated
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