Texas Instruments THS7303EVM Evaluation Module THS7303EVM THS7303EVM 데이터 시트
제품 코드
THS7303EVM
t
w(H)
t
w(L)
t
r
t
f
t
su(1)
t
h(1)
SCL
SDA
t
su(2)
t
h(2)
t
su(3)
t
(buf)
SCL
SDA
Start Condition
Stop Condition
SLOS479B
–
OCTOBER 2005
–
REVISED MARCH 2011
TIMING REQUIREMENTS
(1)
At V
S+
= 2.7 V to 5 V, unless otherwise noted.
STANDARD MODE
FAST MODE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
f
SCL
Clock frequency, SCL
0
100
0
400
kHz
t
w(H)
Pulse duration, SCL high
4
0.6
μ
s
t
w(L)
Pulse duration, SCL low
4.7
1.3
μ
s
t
r
Rise time, SCL and SDA
1000
300
ns
t
f
Fall time, SCL and SDA
300
300
ns
t
su(1)
Setup time, SDA to SCL
250
100
ns
t
h(1)
Hold time, SCL to SDA
0
0
ns
t
(buf)
Bus free time between stop and start conditions
4.7
1.3
μ
s
t
su(2)
Setup time, SCL to start condition
4.7
0.6
μ
s
t
h(2)
Hold time, start condition to SCL
4
0.6
μ
s
t
su(3)
Setup time, SCL to stop condition
4
0.6
μ
s
C
b
Capacitive load for each bus line
400
400
pF
(1)
The THS7303 I
2
C address = 01011(A1)(A0)(R/W). See the
section for more information.
Figure 2. SCL and SDA Timing
Figure 3. Start and Stop Conditions
Copyright
©
2005
–
2011, Texas Instruments Incorporated
7
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