Texas Instruments THS5661A Evaluation Module THS5661EVM THS5661EVM 데이터 시트
제품 코드
THS5661EVM
3
2
1
1
2
Onboard External
Reference Voltage
W3
W4
DAC
EXTLO
EXTIO
BIAS
R14
5 VA
3
2
1
W2
J5
DAC
DAC Clock
CLKOUT
External Clock
Figure 3-5. Jumper Configuration for External Reference
CAUTION
Under no circumstance should the external reference voltage exceed 1.25 V.
3.6
External Clock
The CommsDAC requires an external clock. Two possible external sources for the clock are required by
the CommsDAC. To obtain optimum device performance the user should adhere to the minimum data to
clock transition setup and hold times specified in the data sheet SLAS247A. Violating these timing
parameters may result in increased converter output noise level. The choices are simple and are
discussed in the following sections.
the CommsDAC. To obtain optimum device performance the user should adhere to the minimum data to
clock transition setup and hold times specified in the data sheet SLAS247A. Violating these timing
parameters may result in increased converter output noise level. The choices are simple and are
discussed in the following sections.
3.6.1 External Clock Generation
When connected to an AVDD supply of 5 V and DVDD supply of 5 V, the maximum operating speed of
the CommsDAC is 100 MHz. When the DVDD supply is 3.3 V the maximum clock speed is 67 MHz. The
clock signal comes from either the DSP CLKOUT signal or from the CLK output from a pattern generator
via J5.
the CommsDAC is 100 MHz. When the DVDD supply is 3.3 V the maximum clock speed is 67 MHz. The
clock signal comes from either the DSP CLKOUT signal or from the CLK output from a pattern generator
via J5.
Figure 3-6. External Clock Signal
30
User Configurations
SLAU032C
–
February 2001
–
Revised April 2011
Copyright
©
2001
–
2011, Texas Instruments Incorporated