Texas Instruments TLV320AIC3105 Evaluation Module (EVM) and USB motherboard TLV320AIC3105EVM-K TLV320AIC3105EVM-K 데이터 시트
제품 코드
TLV320AIC3105EVM-K
AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS
T0145-01
WCLK
BCLK
SDOUT
SDIN
t (DO-BCLK)
d
t (DO-WS)
d
t (WS)
d
t (DI)
S
t (DI)
h
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SLAS513B – FEBRUARY 2007 – REVISED DECEMBER 2008
All specifications at 25°C, DVDD = 1.8 V.
IOVDD = 1.1 V
IOVDD = 3.3 V
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
d
(WS)
ADWS/WCLK delay time
50
15
ns
t
d
(DO-WS)
ADWS/WCLK to DOUT delay time
50
20
ns
t
d
(DO-BCLK)
BCLK to DOUT delay time
50
15
ns
t
s
(DI)
DIN setup time
10
6
ns
t
h
(DI)
DIN hold time
10
6
ns
t
r
Rise time
30
10
ns
t
f
Fall time
30
10
ns
NOTE: All timing specifications are measured at characterization but not tested at final test.
Figure 1. I
2
S/LJF/RJF Timing in Master Mode
Copyright © 2007–2008, Texas Instruments Incorporated
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