Texas Instruments TPS65810 Evaluation Module TPS65810EVM TPS65810EVM 데이터 시트

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TPS65810EVM

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INTERRUPT CONTROLLER

SYSTEM STATUS — I

C REGISTERS

TPS65810
TPS65811

SLVS658B – MARCH 2006 – REVISED FEBRUARY 2007

SYSTEM STATUS MONITORED BY SEQUENCING CONTROLLER

When 0

When 1

FAULT

PGOODFAULT_MASK, ADDRESS=07, ALL BITS R/W

Bit name

MASK_PSM1

MASK_PSM2

MASK_PSM3

MASK_PLDO1

MASK_PLDO2

MASK_PLDO3

MASK_PLDO4

MASK_PLDO5

Function

MASK PGOOD

MASK

MASK PGOOD

FAULT BY SM1

PGOOD

FAULT BY

SM3

LDO1

LDO2

LDO3

LDO4

LDO5

SM2

When 0

UNMASKED

When 1

MASKED

The TPS65810 has internal block and overall system status information stored in I

C status registers. The

following subsystems and system parameters are monitored:

•

External power supply status: AC or USB supply detected, AC or USB connected to system, AC/USB OVP

•

Charger status: on/off/suspend, fast charge/pre-charge, termination detected, DPPM on, thermal loop ON

•

Battery pack status: temperature, discharge on/off

•

TPS65810 thermal shutdown

•

ADC status: conversion status, input out of range, ANLG1 high impedance detection

•

Integrated supplies status: output out of regulation (power good fault)

The GPIO1 and GPIO2 pins can be configured as inputs, generating an interrupt request to the host (
INT:HI

→LO) at the GPIO rising or falling edge. The host can use internal the INT_MASK I

C registers to define

which of the monitored status variables triggers an interrupt. When a non-masked system status bit toggles state,
the interrupt controller issues an interrupt, following the steps below:

1. system status bits that caused the interruption are set to HI in registers INT_ACK1 and INT_ACK2

2. An interrupt is sent to the host ( INT:HI

→LO)

Once an interrupt is sent to the host, INT is kept in the LO state and the INT_ACK register contents are latched,
holding the system status that generated the currently issued interrupt request. When an interrupt request is
active (INT = LO) additional changes in non-masked status registers and control signals are ignored, and the
INT_ACK registers are not updated.

The host must write a 0 to the INT_ACK register bit that generated the interrupt in order to set INT = HI and
enable new updates to the INT_ACK registers. If the host stops in the middle of a WRITE or READ operation,
the INT pin stays at the LO level. The TPS65810 has no reset timeout; it is assumed that the host does not leave
INT = LO and the status registers unread for a long time.

The non-masked I

C register bits and internal control signals generate a new interrupt only after INT is set to HI.

The non-masked power-good fault register bits generate a power-good fault when any of the non-masked bits
detects that the monitored output voltage is out of regulation, independently of the INT pin level.

The I

C registers that have system status data are shown below. The HEX address for each register is shown by

the register name, together with the R or W functionality for the register bits. Those registers are valid, after an
initial power up, when the TPS65810 enters the normal operation mode.

SYSTEM STATUS MONITORED BY INTERRUPT CONTROLLER

PGOOD, ADDRESS=02, ALL BITS READ ONLY - POWER UP DEFAULTS SHOW SYSTEM STATUS WHEN EXITING POWER DOWN

Bit name

PGOOD SM1

PGOOD SM2

PGOOD SM3

PGOOD LDO1

PGOOD LDO2

PGOOD LDO3

PGOOD LDO4

PGOOD LDO5

Function

SM1 OUTPUT

SM2 OUTPUT

SM3 OVP

LDO1 OUTPUT

LDO2 OUTPUT

LDO3 OUTPUT

LDO4 OUTPUT

LDO5 OUTPUT

STATUS

When 0

When 1

FAULT

ADC STATUS

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TPS65810 TPS65811