Texas Instruments TPS65810 Evaluation Module TPS65810EVM TPS65810EVM 데이터 시트
제품 코드
TPS65810EVM
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GPIO 3
INTERNAL ADC
CONVERSION STATUS
FIRST
SAMPLE
LAST
SAMPLE
ON
OFF
t
WAIT(TRG)
t
DLY(TRG
)
CONVERSION CYCLE
GPIO 3
INTERNAL ADC
CONVERSION STATUS
FIRST
SAMPLE
LAST
SAMPLE
ON
OFF
T
WAIT(TRG)
T
DLY(TRG)
T
DLY(TRG)
CONVERSION CYCLE
Continuous Conversion Operation (Repeat Mode)
SLVS658B – MARCH 2006 – REVISED FEBRUARY 2007
With the default power-up settings (HOLDOFF=LO, ADC_DELAY register), the TPS65810 executes a
multiple-sample conversion cycle if the first sample is taken when the trigger is at its active level. Subsequent
samples are converted at the end of the wait time, even if the trigger returns to the non-active level. The external
trigger level edge is ignored until the current conversion cycle ends.
multiple-sample conversion cycle if the first sample is taken when the trigger is at its active level. Subsequent
samples are converted at the end of the wait time, even if the trigger returns to the non-active level. The external
trigger level edge is ignored until the current conversion cycle ends.
Figure 49. ADC Conversion Triggered by GPIO3 Positive Edge Triggered Active Level Hi, Holdoff = LC
If the sample conversion needs to be synchronized with an external trigger, during multiple sample conversion
cycles, the control bit HOLDOFF should be set to HI. When the holdoff mode is active, the internal trigger starts
a sample conversion only if the external trigger was detected and is at its active level at the end of the wait time,
as shown in
cycles, the control bit HOLDOFF should be set to HI. When the holdoff mode is active, the internal trigger starts
a sample conversion only if the external trigger was detected and is at its active level at the end of the wait time,
as shown in
Figure 50. ADC Conversion Triggered by GPIO3 Positive Edge Triggered Active Level HI,
Holdoff = HI, Four Sample Cycles
When the multiple sample cycles are executed the host must configure the maximum and minimum limits for the
ADC output using registers DLOLIM1, DLOLIM2, DHILIM1 and DHILIM2. A conversion cycle ends if any
individual conversion result exceeds the maximum limit value or is below the minimum limit value. When an out
of limit conversion is detected an interrupt is sent to the host, and the ADC_STATUS bit on register ADC
READING_HI is set to DONE.
ADC output using registers DLOLIM1, DLOLIM2, DHILIM1 and DHILIM2. A conversion cycle ends if any
individual conversion result exceeds the maximum limit value or is below the minimum limit value. When an out
of limit conversion is detected an interrupt is sent to the host, and the ADC_STATUS bit on register ADC
READING_HI is set to DONE.
The TPS65810 ADC can be set to operate in a continuous conversion mode, with back-to-back conversion
cycles executed. The REPEAT mode is targeted at applications where an input is continuously monitored for a
period of time, and the host must be informed if the monitored input is out of the range set by I
cycles executed. The REPEAT mode is targeted at applications where an input is continuously monitored for a
period of time, and the host must be informed if the monitored input is out of the range set by I
2
C registers
DLOLIM1, DLOLIM2, DHILIM1 and DHILIM2. In REPEAT mode each conversion is started when the ADC trigger
(internal or external) is detected, and a new conversion cycle is started when the current conversion cycle ends.
All the trigger and sampling modes available for normal conversion cycles are available in repeat mode.
Executing I
(internal or external) is detected, and a new conversion cycle is started when the current conversion cycle ends.
All the trigger and sampling modes available for normal conversion cycles are available in repeat mode.
Executing I
2
C read operations to get the ADC readings for average, minimum, maximum and last sample values
is possible in REPEAT mode. However, this is not a recommended operation, as the REPEAT mode does not
generate a DONE status flag making it difficult to synchronize the ADC data reading to the end of a conversion
cycle.
generate a DONE status flag making it difficult to synchronize the ADC data reading to the end of a conversion
cycle.
The recommended use of the REPEAT mode is:
1. Configure the ADC conversion cycle: trigger mode, sample mode, select input signal, etc.
2. Configure the HI and LO limits for the ADC readings
3. Set the ADC_DELAY register bit REPEAT to HI
4. Toggle ADC_DELAY register bit ADC_EN bit from LO to HI
Copyright © 2006–2007, Texas Instruments Incorporated
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