Texas Instruments Evaluation Module for TPS22913C TPS22913CEVM-656 TPS22913CEVM-656 데이터 시트
제품 코드
TPS22913CEVM-656
T
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Board Layout, Schematic, and Bill of Materials
5
Board Layout, Schematic, and Bill of Materials
This section provides the TPS2291xxEVM-656 board layout, schematic, and bill of materials.
5.1
Board Layout
For best performance, all traces should be as short as possible. To be most effective, the input and output
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances
may have on normal and short-circuit operation. Using wide traces for V
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances
may have on normal and short-circuit operation. Using wide traces for V
IN
, V
OUT
, and GND helps minimize
the parasitic electrical effects along with minimizing the case to ambient thermal impedance
, and
show the board layout for the TPS2291xxEVM-656 PCB.
Figure 1. Top Assembly Layer
Figure 2. Top Layer
4
TPS2291xxEVM-656
SLVU501A
–
August 2011
–
Revised January 2012
Copyright
©
2011
–
2012, Texas Instruments Incorporated