Texas Instruments THS7360 Evaluation Module THS7360EVM THS7360EVM 데이터 시트
제품 코드
THS7360EVM
Level
Shift
Internal
Circuitry
+V
S
800 kW
Input
Pin
Level
Shift
Internal
Circuitry
+V
S
800 kW
Input
Pin
Input
0.1 mF
g
m
+V
S
STC LPF
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SLOS674 – JUNE 2010
Because the internal gain is fixed, the gain dictates
go below 0 V, the THS7360 internal control loop
what the allowable linear input voltage range can be
sources up to 6 mA of current to increase the input
without clipping concerns. For example, if the power
voltage level on the THS7360 input side of the
supply is set to 3 V, the maximum output is
coupling capacitor. As soon as the voltage goes
approximately 2.9 V while driving a significant amount
above the 0-V level, the loop stops sourcing current
of current. Thus, to avoid clipping on the SD
and becomes very high impedance.
channels, the allowable input is (2.9 V - 0.12V)/5.6 =
One of the concerns about the STC level is how the
0.5 V. This range is valid for up to the maximum
clamp
reacts
to
a
sync
edge
that
has
recommended
5-V
power
supply
that
allows
overshoot—common in VCR signals, noise, DAC
approximately a (4.9 V – 0.12 V)/5.6 = 0.85 V input
overshoot, or reflections found in poor printed circuit
range while avoiding clipping on the output.
board (PCB) layouts. Ideally, the STC should not
The input impedance of the THS7360 in this mode of
react to the overshoot voltage of the input signal.
operation
is
dictated
by
the
internal,
800-k
Ω
Otherwise, this response could result in clipping on
pull-down resistor, as shown in
. Note that
the rest of the video signal because it may raise the
the internal voltage shift does not appear at the input
bias voltage too much.
pin; it only shows at the output pin.
To help minimize this input signal overshoot problem,
the control loop in the THS7360 has an internal
low-pass filter, as shown in
the control loop in the THS7360 has an internal
low-pass filter, as shown in
. This filter
reduces the response time of the STC circuit. This
delay is a function of how far the voltage is below
ground, but in general it is approximately a 400-ns
delay for the SD channel filters and approximately a
150-ns delay for the SF filters. The effect of this filter
is to slow down the response of the control loop so as
not to clamp on the input overshoot voltage but rather
the flat portion of the sync signal.
delay is a function of how far the voltage is below
ground, but in general it is approximately a 400-ns
delay for the SD channel filters and approximately a
150-ns delay for the SF filters. The effect of this filter
is to slow down the response of the control loop so as
not to clamp on the input overshoot voltage but rather
the flat portion of the sync signal.
As a result of this delay, sync may have an apparent
voltage shift. The amount of shift depends on the
amount of droop in the signal as dictated by the input
capacitor and the STC current flow. Because sync is
voltage shift. The amount of shift depends on the
amount of droop in the signal as dictated by the input
capacitor and the STC current flow. Because sync is
Figure 44. Equivalent DC Input Mode Circuit
used primarily for timing purposes, with syncing
occurring on the edge of the sync signal, this shift is
transparent in most systems.
occurring on the edge of the sync signal, this shift is
transparent in most systems.
INPUT MODE OF OPERATION: AC SYNC TIP
CLAMP
CLAMP
Some video DACs or encoders are not referenced to
ground but rather to the positive power supply. The
resulting video signals are generally at too great a
voltage for a dc-coupled video buffer to function
properly. To account for this scenario, the THS7360
incorporates a sync-tip clamp circuit. This function
requires a capacitor (nominally 0.1
ground but rather to the positive power supply. The
resulting video signals are generally at too great a
voltage for a dc-coupled video buffer to function
properly. To account for this scenario, the THS7360
incorporates a sync-tip clamp circuit. This function
requires a capacitor (nominally 0.1
m
F) to be in series
with the input. Although the term sync-tip-clamp is
used throughout this document, it should be noted
that the THS7360 would probably be better termed as
a dc restoration circuit based on how this function is
performed. This circuit is an active clamp circuit and
used throughout this document, it should be noted
that the THS7360 would probably be better termed as
a dc restoration circuit based on how this function is
performed. This circuit is an active clamp circuit and
Figure 45. Equivalent AC Sync-Tip-Clamp Input
not a passive diode clamp function.
Circuit
The input to the THS7360 has an internal control loop
that sets the lowest input applied voltage to clamp at
that sets the lowest input applied voltage to clamp at
While this feature may not fully eliminate overshoot
ground (0 V). By setting the reference at 0 V, the
issues on the input signal, in cases of extreme
THS7360 allows a dc-coupled input to also function.
overshoot and/or ringing, the STC system should help
Therefore, the sync-tip-clamp (STC) is considered
minimize improper clamping levels. As an additional
transparent because it does not operate unless the
method to help minimize this issue, an external
input signal goes below ground. The signal then goes
capacitor (for example, 10 pF to 47 pF) to ground in
through the same level shifter, resulting in an output
parallel with the external termination resistors can
voltage low level of 120 mV. If the input signal tries to
help filter overshoot problems.
Copyright © 2010, Texas Instruments Incorporated
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