Texas Instruments Evaluation Board for the LM5050-2 LM5050MK-2EVAL/NOPB LM5050MK-2EVAL/NOPB 데이터 시트
제품 코드
LM5050MK-2EVAL/NOPB
VIN
VOUT
GND
OFF
OUT
IN
GATE
LM5050-2
Off
GND
GND
nFGD
nPGD
V
LOGIC
Q1
+
R2
10.0k
10.0k
C1
1.0
1.0
P
F
100V
D1
C2
22
22
P
F
100V
D2
TVS
60V
TVS
60V
OFF
GATE
OUT
IN
1
2
3
6
5
4
nFGD
GND
L
M
5
0
5
0
MK
-2
Status (nPGD) Test Point
There are several factors that may prevent the nFGD pin from going to a logic low in an otherwise good
application. If there is a redundant, parallel, supply in operation, that supply may hold the OUT pin voltage
close enough to the IN pin voltage that the V
application. If there is a redundant, parallel, supply in operation, that supply may hold the OUT pin voltage
close enough to the IN pin voltage that the V
DS(TST)
threshold is not exceeded. Additionally, a high output
capacitance value, or a low load current, may require that a significant amount of time be allowed for the
output capacitance to discharge to the point where the V
output capacitance to discharge to the point where the V
DS(TST)
threshold is exceeded and the nFGD pin
goes low.
Figure 3. MOSFET Test, No Fault
Figure 4. Connection Diagram
Figure 5. Schematic Diagram
3
SNVA435A – November 2010 – Revised May 2013
AN-2051 LM5050-2EVAL Evaluation Board
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