Texas Instruments Three Phase BLDC, PMSM Motor Kit with DRV8301, Encoder and RM46 Safety MCU DRV8301-RM46-KIT DRV8301-RM46-KIT 데이터 시트
제품 코드
DRV8301-RM46-KIT
SLOS719B – AUGUST 2011 – REVISED AUGUST 2013
RECOMMENDED OPERATING CONDITIONS
MIN
TYP MAX
UNITS
PVDD1
DC supply voltage PVDD1 for normal operation
Relative to PGND
6
60
V
PVDD2
DC supply voltage PVDD2 for buck converter
3.5
60
V
C
PVDD1
External capacitance on PVDD1 pin (ceramic cap) 20% tolerance
4.7
µF
C
PVDD2
External capacitance on PVDD2 pin (ceramic cap) 20% tolerance
4.7
µF
C
AVDD
External capacitance on AVDD pin (ceramic cap) 20% tolerance
1
µF
C
DVDD
External capacitance on DVDD pin (ceramic cap) 20% tolerance
1
µF
C
GVDD
External capacitance on GVDD pin (ceramic cap) 20% tolerance
2.2
µF
C
CP
Flying cap on charge pump pins (between CP1 and CP2) (ceramic cap) 20% tolerance
22
220
nF
C
BST
Bootstrap cap (ceramic cap)
100
nF
I
DIN_EN
Input current of digital pins when EN_GATE is high
100
µA
I
DIN_DIS
Input current of digital pins when EN_GATE is low
1
µA
C
DIN
Maximum capacitance on digital input pin
10
pF
C
O_OPA
Maximum output capacitance on outputs of shunt amplifier
20
pF
Dead time control resistor range. Time range is 50ns (-GND) to 500ns (150k
Ω) with a
R
DTC
0
150
k
Ω
linear approximation.
I
FAULT
FAULT pin sink current. Open-drain
V = 0.4 V
2
mA
I
OCTW
OCTW pin sink current. Open-drain
V = 0.4 V
2
mA
V
REF
External voltage reference voltage for current shunt amplifiers
2
6
V
Qg(TOT) = 25 nC or total 30 mA gate
f
gate
Operating switching frequency of gate driver
200
kHz
drive average current
I
gate
Total average gate drive current
30
mA
T
A
Ambient temperature
–40
125
°C
ELECTRICAL CHARACTERISTICS
PVDD = 6 V to 60 V, T
C
= 25°C, unless specified under test condition
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT PINS: INH_X, INL_X, M_PWM (SCS), M_OC (SDI), GAIN(SDO), EN_GATE, DC_CAL
V
IH
High input threshold
2
V
V
IL
Low input threshold
0.8
V
R
EN_GATE
Internal pull down resistor for EN_GATE
100
k
Ω
Internal pull down resistor for high side PWMs
R
INH_X
EN_GATE high
100
k
Ω
(INH_A, INH_B, and INH_C)
Internal pull down resistor for low side PWMs
R
INH_X
EN_GATE high
100
k
Ω
(INL_A, INL_B, and INL_C)
R
SCS
Internal pull down resistor for SCS
EN_GATE high
100
k
Ω
R
SDI
Internal pull down resistor for SDI
EN_GATE high
100
k
Ω
R
DC_CAL
Internal pull down resistor for DC_CAL
EN_GATE high
100
k
Ω
R
SCLK
Internal pull down resistor for SCLK
EN_GATE high
100
k
Ω
OUTPUT PINS: FAULT AND OCTW
V
OL
Low output threshold
I
O
= 2 mA
0.4
V
External 47 k
Ω pull up resistor
V
OH
High output threshold
2.4
V
connected to 3-5.5 V
Leakage Current on Open Drain Pins When
I
OH
1
µA
Logic High (FAULT and OCTW)
Copyright © 2011–2013, Texas Instruments Incorporated
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