Texas Instruments Evaluation Kit for DS99R105 DS99R106 FPD-Link II Serializer and Deserializer Chipset SERDES05-40USB/NO SERDES05-40USB/NOPB 데이터 시트
제품 코드
SERDES05-40USB/NOPB
The SERIALIZER Function
2
The SERIALIZER Function
The Serializer (SER) function generically collects a wide parallel bus plus its clock signal, performs
payload optimization, appends the serial control bits and level translates the high-speed serial signal to
LVDS-like levels. The payload is optimized for serial transmission over AC-coupled interconnects. This
step balances the data being sent to support the AC-coupled transmission. Depending upon the chipset
being used, payload randomization and scrambling is also done to enhance the signal quality across the
link.
payload optimization, appends the serial control bits and level translates the high-speed serial signal to
LVDS-like levels. The payload is optimized for serial transmission over AC-coupled interconnects. This
step balances the data being sent to support the AC-coupled transmission. Depending upon the chipset
being used, payload randomization and scrambling is also done to enhance the signal quality across the
link.
A few options are also supported depending upon the SER device. Various input (parallel) buses are
supported. This ranges from bus width and also signaling physical layer. LVCMOS buses at 3.3V are
supported, with optional 1.8V support on some products. In addition, serializers with FPD-Link (LVDS
based) inputs convert to FPD-Link II (that is, DS99R421 and DS90UR907).
supported. This ranges from bus width and also signaling physical layer. LVCMOS buses at 3.3V are
supported, with optional 1.8V support on some products. In addition, serializers with FPD-Link (LVDS
based) inputs convert to FPD-Link II (that is, DS99R421 and DS90UR907).
3
The DESERIALIZER Function
The Deserializer (DES) function is to recover the clock and data signals and to provide them to the target
device (a display for example). The FPD-Link II DES is very unique as it is able to quickly lock to the serial
stream without the need of a local reference clock or any special training patterns from the SER. These
features set the FPD-Link II SerDes apart from many competing interfaces. They simplify the application,
support hot plugging, and also require less external components (less board space and cost). The DES
even provides a LOCK output signal to allow the system to check serial link status.
device (a display for example). The FPD-Link II DES is very unique as it is able to quickly lock to the serial
stream without the need of a local reference clock or any special training patterns from the SER. These
features set the FPD-Link II SerDes apart from many competing interfaces. They simplify the application,
support hot plugging, and also require less external components (less board space and cost). The DES
even provides a LOCK output signal to allow the system to check serial link status.
A few options are also supported depending upon the DES device selected. Various output (parallel)
buses are supported. This ranges from bus width and also the signaling physical layer. LVCMOS buses at
3.3V are supported, with optional 1.8V support on some products. In addition, deserializers are available
with FPD-Link (LVDS based) outputs (that is, DS90UR908).
buses are supported. This ranges from bus width and also the signaling physical layer. LVCMOS buses at
3.3V are supported, with optional 1.8V support on some products. In addition, deserializers are available
with FPD-Link (LVDS based) outputs (that is, DS90UR908).
4
Serial Payload
The serial payload is optimized for the different chipsets in the FPD-Link II family and also for the
applications they support. A common serial payload to explain as a reference is the 28-bit serial frame
shown in
applications they support. A common serial payload to explain as a reference is the 28-bit serial frame
shown in
. The 28 bits are comprised of: 24 data bits, 2 bits of embedded clock information, and
2 bits of serial control for the link. Thus, for every 24 bits of data, 28 serial bits are sent. This makes the
basic link 24/28 (86%) efficient. This is an important bench mark, as it is always desirable to keep
overhead low. This scheme is also ~30% better than the common data communication 8b/10b scheme
which is 80% efficient. Note that the 24 data bits are modified by the balancing, randomization, and
scrambling. This is done to support the AC coupling on the link, and also to help reduce ISI (Inter-symbol
Interference) effects when sending relatively static data. The two clock bits are fixed, with one bit high (C1)
and one bit low (C0) – note these two are DC balanced as a pair. The two serial control bits, commonly
noted as DCA (A) and DCB (B), provide information to the DES to recover the data and also the link
status and mode. Chipsets supporting 24-bit RGB encode the status of video synchronization signals in
the serial stream.
basic link 24/28 (86%) efficient. This is an important bench mark, as it is always desirable to keep
overhead low. This scheme is also ~30% better than the common data communication 8b/10b scheme
which is 80% efficient. Note that the 24 data bits are modified by the balancing, randomization, and
scrambling. This is done to support the AC coupling on the link, and also to help reduce ISI (Inter-symbol
Interference) effects when sending relatively static data. The two clock bits are fixed, with one bit high (C1)
and one bit low (C0) – note these two are DC balanced as a pair. The two serial control bits, commonly
noted as DCA (A) and DCB (B), provide information to the DES to recover the data and also the link
status and mode. Chipsets supporting 24-bit RGB encode the status of video synchronization signals in
the serial stream.
3
SNLA102B – May 2008 – Revised April 2013
AN-1807 FPD-Link II Display SerDes Overview
Copyright © 2008–2013, Texas Instruments Incorporated